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How to get QSYS to propagate SYSTEM_INFO GENERATION_ID value into composed component

dcattley
Beginner
807 Views

I have created a _hw.tcl component which is a "composed" component that assembles a number of other components into the hierarchy.

 

One of those components happens to be the altera_avalon_sysid_qsys_hw.tcl component.

This component assigns its instance parameter "timestamp" from the SYSTEM_INFO GENERATION_ID value.

 

When the altera_avalon_sysid_qsys_hw.tcl component is instantiated directly in my top level QSYS file, the "timestamp" parameter is properly generated.

 

When that same component is instantiated via my "composing" component, the timestamp is zero.

 

I cannot have my componsing component "set" that parameter because it is declared as "derived".

 

How do I get QSYS to propagate the GENERATION_ID into the composed component?

 

thx,

Dave Cattley

 

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18 Replies
sstrell
Honored Contributor III
792 Views

I don't know that you can do that.  It would probably be easier to create a subsystem design by creating another .qsys file with this component in it.  Remember you can add any .qsys file as a component (a subsystem) in another .qsys.

dcattley
Beginner
785 Views

True enough and that is what I did.  The issue is that some of the customizations and "logic" you can wire into a composed component is much much easier to manage and create in TCL than in QSYS XML.

 

And frankly it seems like a bug.

 

-dave

Nurina
Employee
746 Views

Hi,


Could you attach your design qar file here? To generate a qar file, go to Project>Archive Project


Thanks,

Nurina


dcattley
Beginner
667 Views

Sure.

 

If you build this simple design you will find a top RTl with a QSYS in it.

 

Within the QSYS is a simple design of an I2C to Avalon-MM master attached to:

 

1. A SYSID component directly with ID=1

2. A QSYS Subsystem with a SYSID embedded in it with ID=2

3. A Composed QSYS component with a SYSID embedded in it with ID=3

 

Looking into the generated SYSID instances (source generated by QSYS) it is very easy to see that:

 

(1) has a timestamp properly generated:    assign readdata = address ? 1646427247 : 1;

(2) has a timestamp properly generated:   assign readdata = address ? 1646427247 : 2;

(3) does not have the GENERATION_ID (timestamp) flowing to the instance:   assign readdata = address ? 0 : 3;

 

So basically, this does not work when a component is composed instead of included in a system or subsystem directly (this is taken from altera_avalon_sysid_qsys_hw.tcl).

 

# +-----------------------------------
# | parameters
# |
add_parameter timestamp INTEGER 0
set_parameter_property timestamp DEFAULT_VALUE 0
set_parameter_property timestamp DISPLAY_NAME "Time stamp"
set_parameter_property timestamp TYPE INTEGER
set_parameter_property timestamp UNITS None
set_parameter_property timestamp AFFECTS_GENERATION true
set_parameter_property timestamp HDL_PARAMETER false
set_parameter_property timestamp SYSTEM_INFO GENERATION_ID
set_parameter_property timestamp ENABLED false
set_parameter_property timestamp VISIBLE false
set_parameter_property timestamp DERIVED true
# |
# +-----------------------------------

 

-dave

dcattley
Beginner
668 Views

Sure.

 

If you build this simple design you will find a top RTl with a QSYS in it.

 

Within the QSYS is a simple design of an I2C to Avalon-MM master attached to:

 

1. A SYSID component directly with ID=1

2. A QSYS Subsystem with a SYSID embedded in it with ID=2

3. A Composed QSYS component with a SYSID embedded in it with ID=3

 

Looking into the generated SYSID instances (source generated by QSYS) it is very easy to see that:

 

(1) has a timestamp properly generated:    assign readdata = address ? 1646427247 : 1;

(2) has a timestamp properly generated:   assign readdata = address ? 1646427247 : 2;

(3) does not have the GENERATION_ID (timestamp) flowing to the instance:   assign readdata = address ? 0 : 3;

 

So basically, this does not work when a component is composed instead of included in a system or subsystem directly (this is taken from altera_avalon_sysid_qsys_hw.tcl).

 

# +-----------------------------------
# | parameters
# |
add_parameter timestamp INTEGER 0
set_parameter_property timestamp DEFAULT_VALUE 0
set_parameter_property timestamp DISPLAY_NAME "Time stamp"
set_parameter_property timestamp TYPE INTEGER
set_parameter_property timestamp UNITS None
set_parameter_property timestamp AFFECTS_GENERATION true
set_parameter_property timestamp HDL_PARAMETER false
set_parameter_property timestamp SYSTEM_INFO GENERATION_ID
set_parameter_property timestamp ENABLED false
set_parameter_property timestamp VISIBLE false
set_parameter_property timestamp DERIVED true
# |
# +-----------------------------------

 

The HW.TCL for the "composed" component is this:

# _hw.tcl file for composed
package require -exact qsys 14.0

# module properties
set_module_property NAME {composed}
set_module_property DISPLAY_NAME {Composed sysid}

# default module properties
set_module_property VERSION {1.0}
set_module_property GROUP {dcattley}
set_module_property DESCRIPTION {Composed component with sysid embedded}
set_module_property AUTHOR {dcattley@velodyne.com}

set_module_property COMPOSITION_CALLBACK compose
set_module_property opaque_address_map false

# +-----------------------------------
# | parameters
# |
add_parameter id INTEGER 0
set_parameter_property id DEFAULT_VALUE 0
set_parameter_property id DISPLAY_NAME "32 bit System ID"
set_parameter_property id TYPE INTEGER
set_parameter_property id UNITS None
set_parameter_property id AFFECTS_GENERATION true
set_parameter_property id HDL_PARAMETER false
add_parameter timestamp INTEGER 0
set_parameter_property timestamp DEFAULT_VALUE 0
set_parameter_property timestamp DISPLAY_NAME "Time stamp"
set_parameter_property timestamp TYPE INTEGER
set_parameter_property timestamp UNITS None
set_parameter_property timestamp AFFECTS_GENERATION true
set_parameter_property timestamp HDL_PARAMETER false
set_parameter_property timestamp SYSTEM_INFO GENERATION_ID
set_parameter_property timestamp ENABLED false
set_parameter_property timestamp VISIBLE false
set_parameter_property timestamp DERIVED true
# |
# +-----------------------------------

# +-----------------------------------
# | display items
# |
add_display_item "" id PARAMETER
set_display_item_property id DISPLAY_HINT hexadecimal
add_display_item "Description" id text "Please use hexadecimal numbers only in System ID."
# |
# +-----------------------------------

proc compose { } {
# Collect parameter values into local variables
foreach var [ get_parameters ] {
set $var [ get_parameter_value $var ]
}

send_message info "composed:id = $id"

# Instances and instance parameters
# (disabled instances are intentionally culled)
add_instance clk clock_source 18.1
set_instance_parameter_value clk {clockFrequency} {50000000.0}
set_instance_parameter_value clk {clockFrequencyKnown} {0}
set_instance_parameter_value clk {resetSynchronousEdges} {NONE}

add_instance csr altera_avalon_mm_bridge 18.1
set_instance_parameter_value csr {ADDRESS_UNITS} {SYMBOLS}
set_instance_parameter_value csr {ADDRESS_WIDTH} {10}
set_instance_parameter_value csr {DATA_WIDTH} {32}
set_instance_parameter_value csr {LINEWRAPBURSTS} {0}
set_instance_parameter_value csr {MAX_BURST_SIZE} {1}
set_instance_parameter_value csr {MAX_PENDING_RESPONSES} {4}
set_instance_parameter_value csr {PIPELINE_COMMAND} {1}
set_instance_parameter_value csr {PIPELINE_RESPONSE} {1}
set_instance_parameter_value csr {SYMBOL_WIDTH} {8}
set_instance_parameter_value csr {USE_AUTO_ADDRESS_WIDTH} {1}
set_instance_parameter_value csr {USE_RESPONSE} {0}

add_instance sysid altera_avalon_sysid_qsys 18.1
set_instance_parameter_value sysid {id} $id


# connections and connection parameters
add_connection clk.clk csr.clk clock

add_connection clk.clk sysid.clk clock

add_connection clk.clk_reset csr.reset reset

add_connection clk.clk_reset sysid.reset reset

add_connection csr.m0 sysid.control_slave avalon
set_connection_parameter_value csr.m0/sysid.control_slave arbitrationPriority {1}
set_connection_parameter_value csr.m0/sysid.control_slave baseAddress {0x0000}
set_connection_parameter_value csr.m0/sysid.control_slave defaultConnection {0}

# exported interfaces
add_interface clk clock sink
set_interface_property clk EXPORT_OF clk.clk_in
add_interface csr avalon slave
set_interface_property csr EXPORT_OF csr.s0
add_interface reset reset sink
set_interface_property reset EXPORT_OF clk.clk_in_reset

# interconnect requirements
set_interconnect_requirement {$system} {qsys_mm.clockCrossingAdapter} {HANDSHAKE}
set_interconnect_requirement {$system} {qsys_mm.enableEccProtection} {FALSE}
set_interconnect_requirement {$system} {qsys_mm.insertDefaultSlave} {FALSE}
set_interconnect_requirement {$system} {qsys_mm.maxAdditionalLatency} {1}
}

## --end-- ##

 

regards,

Dave Cattley

 

dcattley
Beginner
724 Views

i'm not sure why but my reply to this with the QAR does not seem to be showing up ...

dcattley
Beginner
723 Views

third try?

dcattley
Beginner
723 Views

The design has three SYSIDs in it.  The one in the "composed" component hierarchy does not get the GENERATION_ID (timestamp) value propagated into it. 

Nurina
Employee
654 Views

Thank you. May I know which version of Quartus you're using?


dcattley
Beginner
571 Views

@Nurina wrote:

Thank you. May I know which version of Quartus you're using?



Quartus 18.1.1

 

From the QSF file in the QAR:

# -------------------------------------------------------------------------- #
#
# Quartus Prime
# Version 18.1.1 Build 646 04/11/2019 SJ Standard Edition
# Date created = 16:33:54  March 04, 2022
#
# -------------------------------------------------------------------------- #
...
# Project-Wide Assignments
# ========================
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 18.1.1
set_global_assignment -name PROJECT_CREATION_TIME_DATE "15:03:07  MARCH 04, 2022"
set_global_assignment -name LAST_QUARTUS_VERSION "18.1.1 Standard Edition"

From the QPF file in the QAR:

# -------------------------------------------------------------------------- #
#
# Quartus Prime
# Version 18.1.1 Build 646 04/11/2019 SJ Standard Edition
# Date created = 15:03:07  March 04, 2022
#
# -------------------------------------------------------------------------- #

 

Nurina
Employee
501 Views

Hi, please note that we are currently investigating the problem. I will let you know if we have any updates.


Regards,

Nurina


Nurina
Employee
484 Views

Hi, please note that we are currently investigating the problem. I will let you know if we have any updates.


Regards,

Nurina


Nurina
Employee
434 Views

Hi, I've reported this problem to our internal team. I will let you know of any updates.


Nurina
Employee
364 Views

Hi, please note that we are currently investigating the problem. I will let you know if we have any updates.


Regards,

Nurina



Nurina
Employee
339 Views

Hi, please note that we are currently investigating the problem. I will let you know if we have any updates.


Regards,

Nurina


dcattley
Beginner
321 Views
Nurina
Employee
305 Views

Hi, please note that we are currently investigating the problem. I will let you know if we have any updates.


Regards,

Nurina


Nurina
Employee
229 Views

Hi,


We had feedback this issue to our engineering. However, due to different priority on hand in engineering, the fix will take some time. We are sorry to inform this.


I will put this case to close pending. Please post a response in the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you with your follow-up questions.


Regards,

Nurina


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