DDR-interface pins

[Altera_Forum]

Hello 

 I have a pcb with ddr pins (one dqs, one dm and two dq on 16-bit) assigned to wrong pins of Cyclone3. I think that altmemphy can work at lower frequence, am I right?  Quartus report that it is error and don't finished compilation   How can I compile design?

[Altera_Forum]

ALT_MEMPHY is a stubborn thing and your compilation will keep failing, no matter what frequency, because the incorrectly routing pins can not be connected to the internal resources used by ALT_MEMPHY. 

Depending on what you expect to do with the board : 

• If you want to use other Altera IP you have to correct the PCB 
• In the other case you could develop your own phy, together with your own controller, which is a rather big undertaking. 

I'm currently in the process of developing my own Phy/Controller combo, as I find the resources used by the HPC II and the ALT_MEMPHY absolutely ridiculous, certainly if you one is using DDR2 at the lower frequencies of 125 and 167 MHz. But for safety (and perhaps sanity) I have made sure the ALT_MEMPHY will work as well.

[Altera_Forum]

Thank you, you are right. I am looking for DDR-controller on opencores 

 Cyclone3 have upper frequency for DDR-controller 200 MHz, so I think that mobile DDR is more suitable.   Current design isn't my own so my task is force it to work.

[Altera_Forum]

With hindsight, after a night of sleep, I must admit that my advice isn't that good. Even if you fabricate your own PHY (and controller) you (probably) need a fed-back clock signal to register the incoming data. In principle you can use any pin and designate it as 'inout' but that is not exactly the same as feeding a clock out on a pin and taking it back in on another pin. (My tests so far haven't been very conclusive about that). 

So the safest way out is to correct the PCB, I guess.

[Altera_Forum]

i am also trying to use altmemphy in cyclone 3 de0 kit but error on fitter anybody help me