DDR2 Timing

Intel® Quartus® Prime Software

Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)

DDR2 Timing

876 Views

I have a Cyclone IV design with Nios and a DDR2-RAM connected to the Nios.

There is an .sdc file generated by Quartus named "CPU1_DDR2_phy_ddr_timing.sdc". I think it is generated with a script.

Do I still need to constrain the timing of the DDR2?

Thanks for your support!

Link Copied

0 Replies

Community support is provided during standard business hours (Monday to Friday 7AM - 5PM PST). Other contact methods are available here.

Intel does not verify all solutions, including but not limited to any file transfers that may appear in this community. Accordingly, Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade.

For more complete information about compiler optimizations, see our Optimization Notice.