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Hi everyone!
I'm currently working on an implementation that requires me to store packets into the SDRAM then fetch it when it is optimal to transmit. I am having trouble on making it work though. The way I understand it, I have two options.- Use NIOS through QSYS then access the memory using C programming.
- Use AVALON INTERFACE and MegaWizard to generate the necessary IP.
i want to extract the data from the memory to a logic outside the nios system. in essence, i am just using the nios to access the memory because this is the easier tutorial that i have found online. however, it lacks the succeeding steps.
for the avalon:
AVALON MEMORY MAP INTERFACE Chapter 3. Avalon Memory-Mapped Interfaces http://www.altera.com/literature/manual/mnl_avalon_spec.pdf Embedded Peripherals IP USER GUIDE Chapter 2. SDRAM Controller Core http://www.altera.com/literature/ug/ug_embedded_ip.pdf External Memory Interface Handbook - Volume 2: Design Guidelines Chapter 9. Implementing and Parameterizing Memory IP http://www.altera.com/literature/hb/external-memory/emi_plan.pdf From this, I have deduced that the SDRAM controls will be handled by the IP built by Altera, and the only thing that I should have problem is utilizing the Avalon-MM Slave Port. This might be a good idea for developers who are already familiar with altera because the Avalon interface is used in many IP but since this is my first time to use such interface, I am lost on how to proceed. i know that this is a more straight forward approach but i can't find the right timing diagram to create an fsm that will utilize the signals. moreover, i need more information on each control and data signals. on top of that, during the creation of the ip with megawizard, i don't have any idea on what to put into the parameters of the sdram because the de2-115 did not specify what chip it is. Here are the information that I know about the SDRAM in DE2-115.
- DDR2 - 128MB
- 16 data lines shared for both SDRAM making it access 32 bit of data per address locations.
- It has 13 address lines and 2 address lines for the banks.
- Address Banks = (2^13) (2^10) (2^2) = 8192 1024 * 4 = 33554432 address locations = 32M
- 32M words x 32 bits/word = 1028 Mbits = 128MB
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It's easy: every byte on Avalon-MM interface is addressed. So you just need to think about write/read operations on Avalon bus. The rest is done by DDR2 controller. On chapter 3 you have all the needed info to design your Avalon Master: http://www.altera.com/literature/manual/mnl_avalon_spec.pdf
The datasheets (for SDRAM too) for your board are here: http://www.altera.com/education/univ/materials/boards/de2-115/unv-de2-115-board.html -> a *.zip file for download in the bottom.- Mark as New
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Thank you sir linas for pointing out the .zip file. I missed that one. I just realized that the SDRAM is not a DDR. I think the ones in the controller in the MegaWizard will not work for the SDRAM of the DE2-115. Do you have any idea on how to complete the logic with the AVALON interface using QSYS?
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Do you mean "SRAM is not a DDR"? Because SDRAM is DDR.
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I mean there is no mention of DDR in the Datasheet. I assumed that the SDRAM is a Single Data Rate DRAM. Please correct me if I am wrong.
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I'm referring to this difference:
Single data rate (SDR) SDRAM is the older type of memory, commonly used in computers prior to 2002. Double data rate (DDR) SDRAM hit the mainstream computer market around 2002 and is a straightforward evolution from SDR SDRAM. The most significant difference between DDR and SDR is that DDR reads data on both the rising and falling edges of the clock signal, enabling a DDR memory module to transfer data twice as fast as an SDR memory module. SOURCE: http://www.crucial.com/kb/answer.aspx?qid=3773- Mark as New
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SDRAM stands for synchronous dynamic random access memory and says nothing about data rate. It may be single data rate or double data rate. SRAM stands for static random access memory, what says us, that it does not need refresh.
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Yes, I know. However, since the datasheet did not say that the SDRAM is a DDR then I assumed that it is an SDR.
--- Single data rate (SDR) SDRAM is the older type of memory, commonly used in computers prior to 2002. Double data rate (DDR) SDRAM hit the mainstream computer market around 2002 and is a straightforward evolution from SDR SDRAM. The most significant difference between DDR and SDR is that DDR reads data on both the rising and falling edges of the clock signal, enabling a DDR memory module to transfer data twice as fast as an SDR memory module. SOURCE: crucial<dot>com -- I can't post links without the moderator checking the content for now.- Mark as New
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There is written in datasheet, that inputs are acquired only on rising edge of the CLK signal.
QSYS has a controller for SDRAM memory, so you must write Avalom Master to access it. Or use Nios II. Or use these templates: http://www.altera.com/support/examples/nios2/exm-avalon-mm.html- Mark as New
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--- Quote Start --- There is written in datasheet, that inputs are acquired only on rising edge of the CLK signal. --- Quote End --- That means it is an SDR SDRAM right sir? --- I do want to use the Avalon interface and that is my main problem now. With the device being a SDR SDRAM, there is no controller in MegaWizard which is pretty straight forward in terms of creating IPs unlike QSYS that you have to make the connections. I don't want to use the NIOS because I want a more straight forward approach but I can't find the proper AVALON component to match the "Avalon Memory Mapped Master" of NIOS. As stated in my initial post, after completing the system with NIOS, I have no clue on how to proceed on using the SDRAM memory through NIOS. I am still looking into this if this proves to be an easier route than understanding the AVALON MM Interface but I can't find a good tutorial on doing either. Thank you for you insights :)
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I clearly see in my QSYS a component called "SDRAM Controller". You have 2 options: export Avalon MM interface from QSYS to Quartus or add your custom peripheral to QSYS.
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I also have the SDRAM Controller but I don't know which one of the following Avalon to use or am I looking in the right place?
- Avalon-MM Clock Crossing Bridge
- Avalon-MM DDR Memory Half Rate Bridge
- Avalon-MM Pipeline Bridge
- Avalon-MM Tristate Bridge
- JTAG to Avalon Master Bridge
- SPI Slave to Avalon Master Bridge
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Look for "Click to export" in Qsys. So you can make the whole Avalon MM slave interface available in Quartus.
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--- Quote Start --- Look for "Click to export" in Qsys. So you can make the whole Avalon MM slave interface available in Quartus. --- Quote End --- You mean this set of codes will appear? That did remove the error "must be connected to an avalon-MM master." I can export this now.
.sdram_0_s1_address (<connected-to-sdram_0_s1_address>), // sdram_0_s1.address
.sdram_0_s1_byteenable_n (<connected-to-sdram_0_s1_byteenable_n>), // .byteenable_n
.sdram_0_s1_chipselect (<connected-to-sdram_0_s1_chipselect>), // .chipselect
.sdram_0_s1_writedata (<connected-to-sdram_0_s1_writedata>), // .writedata
.sdram_0_s1_read_n (<connected-to-sdram_0_s1_read_n>), // .read_n
.sdram_0_s1_write_n (<connected-to-sdram_0_s1_write_n>), // .write_n
.sdram_0_s1_readdata (<connected-to-sdram_0_s1_readdata>), // .readdata
.sdram_0_s1_readdatavalid (<connected-to-sdram_0_s1_readdatavalid>), // .readdatavalid
.sdram_0_s1_waitrequest (<connected-to-sdram_0_s1_waitrequest>) // .waitrequest
From here, I can just work on the logic using the avalon interface guide right? Thank you for sharing your knowledge on this. I have a simple request though. I have read that guide but do you know any straight forward guide that could help me develop my design? An example will be of great help to me :)
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I am not sure at this point if I need to add a PLL for the SDRAM. With the NIOS implementation, the PLL was crucial.
--- Quote Start --- The clock skew depends on physical characteristics of the DE2-115 board. For proper operation of the SDRAM chip, it is necessary that its clock signal, DRAM_CLK, leads the Nios II system clock, CLOCK_50, by 3 nanoseconds. This can be accomplished by using a phase-locked loop (PLL) circuit which can be manually created using the MegaWizard plug-in. It can also be created automatically using the Clock Signals IP core provided by the Altera University Program. We will use the latter method in this tutorial. --- Quote End ---- Mark as New
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address, writedata, readdata, readdatavalid, read_n and write_n are self explaining singals. byteenable_n can be constant '0'. chipselect can be tied to '1' if only your peripheral has access to that SDRAM. slave asserts waitrequest when it is busy.
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--- Quote Start --- address, writedata, readdata, readdatavalid, read_n and write_n are self explaining singals. byteenable_n can be constant '0'. chipselect can be tied to '1' if only your peripheral has access to that SDRAM. slave asserts waitrequest when it is busy. --- Quote End ---
wire sdram_avl_address; // sdram_avl.address
wire sdram_avl_byteenable_n; // .byteenable_n
wire sdram_avl_chipselect; // .chipselect
wire sdram_avl_writedata; // .writedata
wire sdram_avl_read_n; // .read_n
wire sdram_avl_write_n; // .write_n
wire sdram_avl_readdata; // .readdata
wire sdram_avl_readdatavalid; // .readdatavalid
wire sdram_avl_waitrequest; // .waitrequest
wire reset_reset_n; // reset.reset_n
Looking at the instantiated code, I think you were right when you said that it is straightforward. I started with DDR2 IP Core which has complicated address signals. The way I see it, the addressing concatenated the rows, columns, and bank which has 13, 10, and 2 bits respectively to create an address signal of 25 bits. Moreover, the write and read data has the same word length as the one in the SDRAM. I'll work this thing out. Many thanks for your insights sir Linas.
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Hi smdumla!
you had any progress in your code. I'm trying to do the same thing, but I'm finding some inconsistencies!- Subscribe to RSS Feed
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