Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
Announcements
FPGA community forums and blogs on community.intel.com are migrating to the new Altera Community and are read-only. For urgent support needs during this transition, please visit the FPGA Design Resources page or contact an Altera Authorized Distributor.
17268 Discussions

DE4_230_D5M example - DDR2 controller

Altera_Forum
Honored Contributor II
‎06-29-2012 03:24 PM
1,111 Views

Hi, 

 

 

I bought a D5M camera and a DE4 board.  

With the D5M camera I received a CD-ROM with some circuits examples. I would compile one of these projects named DE4_230_D5M_DVI. When I synthesize the design, I have the following errors: 

 

 

Error: Can't find valid feature line for core DDR2_SODIMM_Write_Port (535C_0012) in current license 

Error (10003): Can't open encrypted VHDL or Verilog HDL file "C:/Terasic/DE4_Install/DE4_Install/DE4_230_D5M_DVI/DDR2_SODIMM_Write_Port.v" -- current license file does not contain a valid license for encrypted file. 

 

 

I use Quatus II (12.0) with a full license.  

How can I solve my problem?  

 

thank you 

 

Mary
0 Kudos

Link Copied

1 Reply
Altera_Forum
Honored Contributor II
‎07-23-2012 11:20 AM
401 Views

Hello Mary,  

 

you need licence file for the DE4 cam example design. You have to contact terasic support and order the licence. 

 

cheers! 

 

Martin
0 Kudos
Copy link
Reply

Community support is provided Monday to Friday. Other contact methods are available here.

Intel does not verify all solutions, including but not limited to any file transfers that may appear in this community. Accordingly, Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade.

For more complete information about compiler optimizations, see our Optimization Notice.