Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
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DLATCH inferred as combinational loop on a specific condition

Balaji_G_Intel
Employee
772 Views

Warning (332125): Found combinational loop of 2 nodes File...

Warning (335091): The Timing Analyzer found 1 latches that cannot be analyzed as synchronous elements. For more details, run the Check Timing command in the Timing Analyzer or view the "User-Specified and Inferred Latches" table in the Synthesis report.

 

 

One of the condition the dlatch is not included as part of timing node for analysis, instead its treated as combinational loop

 

I have a specific testcase to reproduce. Please connect with me directly and i can provide the test case.

 

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5 Replies
sstrell
Honored Contributor III
542 Views

Can you provide the RTL code? It sounds like you've accidentally inferred one or more latches in your design, which should be avoided.

 

#iwork4intel

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Balaji_G_Intel
Employee
542 Views

I'll ping you to share the code.

Thanks

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KhaiChein_Y_Intel
542 Views

Hi,

 

Can you share the design.qar to reproduce the error?

 

Thanks.

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Balaji_G_Intel
Employee
542 Views

As its a internal case, Please send a email and i'll share qar directly.

 

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KhaiChein_Y_Intel
542 Views

Hi,

 

I have sent an email to you. Please let me know if you did not received.

 

Thanks.

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