DMA controller Intel FPGA IP

[Fuad1]

To whom it may concern,

I'm planning to use the Intel DMA controller FPGA IP (Avalon DMA) in my Cyclone V design. In this DMA IP documentation (chapter 30 of the document provided by the link below), the end-of-packet signal is mentioned several times. Where it is mentioned that it can be asserted by the write and read ports to end the transaction.

My question is: How can I assert the end-of-packet signal to end a transaction because I don't see this signal in the IP block in platform designer?

https://www.intel.com/content/www/us/en/docs/programmable/683130/21-2/introduction.html

Regards,

[sstrell]

That's weird because EOP only makes sense in the context of Avalon streaming, not memory mapped.  There's no parameter to use streaming instead of memory-mapped, so it's unclear what is being referred to.

[ShengN_Intel]

Hi,

As mentioned by SStrell, eop only exists in Avalon ST.

The DMA Controller Core topic in document Embedded Peripherals is general topic. Actually there're two DMA Controller, one is DMA Controller Intel FPGA IP under Basic Functions and another one is DMA Controller under Video. If check both DMA Controller Intel FPGA IP and DMA Controller details, both point to the same user guide.

The end-of-packet signal refers to DMA Controller under Video which uses Avalon ST.

Thanks,

Regards,

Sheng