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DPRAM IP configuration in Quartus 19.1 for Cyclone 10 implementation

CFlor36
Beginner
215 Views

Hi

I am working of Quartus 19.1 lite and I want to make an implementation on device 10CL016YU484.

There is a dpram in my design and I cannot access to all parameters to configure this block

I want an asynch clear for write clock and an asynch clear for read clock, and I only can set an asynch clear for the read one.

How can I access the aynch clear for the write clock domain ?

Regards

Florent

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1 Reply
RichardTanSY_Intel
151 Views

Based on the UG, only ‘raddress’, ‘q_a’, or ‘q_b’ are available for asynchronous clear in the RAM 2-port IP parameters setting.

I don't think there is an option for asynchronous clear for the write clock domain.

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_ram_rom.pdf#page=30

 

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