I am working of Quartus 19.1 lite and I want to make an implementation on device 10CL016YU484.
There is a dpram in my design and I cannot access to all parameters to configure this block
I want an asynch clear for write clock and an asynch clear for read clock, and I only can set an asynch clear for the read one.
How can I access the aynch clear for the write clock domain ?
Based on the UG, only ‘raddress’, ‘q_a’, or ‘q_b’ are available for asynchronous clear in the RAM 2-port IP parameters setting.
I don't think there is an option for asynchronous clear for the write clock domain.