Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
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DSPBuilder Reset inputs in Quartus BDFs

Honored Contributor II

The new symbols from DSP Builder all have clock and reset inputs plus whatever user I/Os you've added. My question is what do I tie the reset inputs to. I don't have an external reset, I'm depending on the internal FPGA circuitry to boot up accordingly. I've seen them just tied to ground but that seems potentially hazardous. Xilinx gave you a GSR module to use, but I haven't seen anything similar in Altera.

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