Debounce Verilog ( I have some questions)

[Altera_Forum]

hello everyone. i'm new to verilog programming. i have some questions on debouncer. I already get the concept of debouncing. but how do i compute for the length of the register that i would be using. 

 i would be using this for a pushbutton on DE1. evrytime i press the button, there are still a lot of increments even with this debouncer. i am using 24MHz clock.   here's my code:  module dbc(pbnoisy, clk, pbclean);   input wire pbnoisy, clk; output reg pbclean;   parameter N=8;   reg [ N - 1 : 0 ] ctr;   always @(posedge clk) begin  ctr [ N -1 : 0 ] <= {ctr[N-2:0] , pbnoisy};  if ( ctr[N-1:0] == 8'b00000000)  pbclean <= 1;  else  if ( ctr[N-1:0] == 8'b11111111)  pbclean <= 0;  else pbclean <= pbclean; end endmodule  please help. thanks

[Altera_Forum]

The filter time must be longer than the bouncing settling time. 

An unfiltered pushbutton is likely to have bouncing spikes extending in the 100us - 1ms range, so you need to sample the level for a few ms. With a 24MHz and 8 samples you achieve a filter "low pass" frequency of about 3MHz which is totally ineffective. You must use a lower frequency sampling: if you keep the 8 samples, choose a sample rate around 10kHz.

[Altera_Forum]

--- Quote Start ---  The filter time must be longer than the bouncing settling time. An unfiltered pushbutton is likely to have bouncing spikes extending in the 100us - 1ms range, so you need to sample the level for a few ms. With a 24MHz and 8 samples you achieve a filter "low pass" frequency of about 3MHz which is totally ineffective. You must use a lower frequency sampling: if you keep the 8 samples, choose a sample rate around 10kHz.  --- Quote End ---     thanks. but, what do you mean? i change my 24MHz clock? or the number of samples? i tried increasing the number of samples, still i get same results. please help.

[Altera_Forum]

You can keep on using the 24mhz clock and 8 sample. You can simply define a counter and inside the always @(posedge clk) process you place the sampling in a conditional statement. For example: 

counter <= counter + 1; if (counter == 1000)  begin   <sample here the input>  counter <= 0;  end

[Altera_Forum]

--- Quote Start ---  You can keep on using the 24mhz clock and 8 sample. You can simply define a counter and inside the always @(posedge clk) process you place the sampling in a conditional statement. For example: counter <= counter + 1; if (counter == 1000)  begin   <sample here the input>  counter <= 0;  end  --- Quote End ---     dude please help. i changed my debouncer to this one:   module dbc(pbnoisy, clk, pbclean);   input wire pbnoisy, clk; output reg pbclean;   parameter N=8;   reg [ N - 1 : 0 ] ctr; reg [ 12 : 0] M;   initial begin  M <= 0;  pbclean <= 0; end always @(posedge clk) begin  M = M + 1;  if (M == 3_000_000) pbclean <= 1;  else pbclean <= 0; end endmodule     and on my main code i called it by this:   wire pb3; dbc dbc3( !PB[3], ClOCK_24A, pb3);    also i used this for incrementing:  if (pb3)  begin  ctr <= ctr + 1;  end      however, nothing happens when i press PB[3]. what should be done?

[Altera_Forum]

--- Quote Start ---   however, nothing happens when i press PB[3]. what should be done?  --- Quote End ---   That's correct!  According to your code nothing should happen.  You'd better consider how the input signal 'pbnoisy' is supposed to affect the output... since you don't use it. Moreover, I'd reset M when you reach the threshold condition, otherwise you'd have one-shot operation.