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Altera_Forum
Honored Contributor I
1,463 Views

Delaying all incoming signals by 2 ms using VHDL

Hi to all, I'm a finance student and I'm also interested in electronics, these days I do program because my limited of knowledge of this, so ask for help in here.I have two incoming signals that I want to test the coincidence between. But, I first want to delay all of the signals from one channel by the period at which the signals are being sent (2 ms) and compare the coincidence this way. So basically, I want to store the real-time information for 2 ms and then replay it as soon as it finishes collecting, and continue this process on and on. Is this feasible using an FPGA? I was thinking of using one of the following: 

 

 

outputA <= inputA after 2 ms; 

outputA <= inertial inputA after 2 ms; 

outputA <= transport inputA after 2 ms; 

 

 

but from what I understand, these are only used for simulation? What other method(s) would be better to accomplish such a task? Using a shift register, or something similar? 

 

 

edit: 

 

 

In my setup, I have two detectors (single photon counting modules) that convert photons of light into a digital signal (3.3V, about 50 ns pulse width). The signals are then being sent to an altera de2 board (https://www.altera.com/solutions/partners/partner-profile/terasic-inc-/board/altera-de2-115-developm...), where they are tested with AND gates for coincidence (note, the signals are being shortened from 50 ns to around 15 to 25 ns (http://www.kynix.com/detail/30942/ns.html) beforehand, with internal logic and no timing loss). The clock on this board runs at 50 MHz, which has a rising edge every 20 ns. The laser sends a pulse every 2 ms. The real counts and random noise counts from these detectors follow no clock, so they will not necessarily share a rising or falling edge exactly the 50 MHz clock. Testing the coincidence is not the issue I'm having, what I need to do now is delay one of the signals by the period of the laser and test the coincidence then. Because the laser is so slow, it is impractical to delay the signal phisically (it would require around 1 km of optical fiber). So, I am trying to do this delay through the FPGA itself. Now to rephrase my questions: 

 

 

(1) Is it possible to maintain temporal accuracy (down to very few nanoseconds) when using a FIFO buffer to delay one of the incoming signals, or will sending the signals into the buffer lose that accuracy and only share rising/falling edges with my clock? (Does the buffer say that block of data is either entirely zero or entirely 1, depending on whether the signal was in a high or low state at the rising edge of the clock when it collects the data?) 

 

 

(2) How would I begin to write code for such a buffer, is this something I can find a copy of online or would there be any "buffer wizards" that I can create using a VHDL program like Quartus II? 

Thanks all!:)
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6 Replies
Altera_Forum
Honored Contributor I
42 Views

Yes those constructs are used only for simulation, but they do not work as buffers either. They are meant to model the delay through a wire, so any other assignment in the mean time will override any previous assignment. 

For your test you probably want to detect the edge of the pulses and then start off a counter to time the delay between the pulses. You can only be as accurate as the clock you are using for any logic, so for your case you can only be accurate to the nearest 20 ns. 

 

2. Quartus has many IP blocks avaialble for free. See https://www.altera.com/support/literature/lit-ip.html for a looong list of altera IP. But from what you describe, you probably dont need a buffer, more like a detector and a counter.
Altera_Forum
Honored Contributor I
42 Views

Thanks for your help and offered resources.

Altera_Forum
Honored Contributor I
42 Views

you could use a pll or an external clock to create a faster clock, which gives greater resolution.

Altera_Forum
Honored Contributor I
42 Views

You might find this discussion valuable (http://zipcpu.com/dsp/2017/11/10/delayw.html), http://zipcpu.com/dsp/2017/11/10/delayw.html (http://zipcpu.com/dsp/2017/11/10/delayw.html), it describes how to build a delay line--just what you are looking for. The only difficulty is that the discussion revolves around a varilog implementation. Still, I think you'll find some valuable points to work from there. 

 

Dan
Altera_Forum
Honored Contributor I
42 Views

 

--- Quote Start ---  

(1) Is it possible to maintain temporal accuracy (down to very few nanoseconds) when using a FIFO buffer to delay one of the incoming signals, or will sending the signals into the buffer lose that accuracy and only share rising/falling edges with my clock? (Does the buffer say that block of data is either entirely zero or entirely 1, depending on whether the signal was in a high or low state at the rising edge of the clock when it collects the data?) 

 

--- Quote End ---  

 

 

This is going to be the tricky part ... to maintain 2ns sampling accuracy requires a 500MHz clock to the sampling circuit (or 3ns at 333MHz). Depending upon the device this may or may not be achievable; it is at the high (or beyond) end of most device PLLs. 

 

The maximum clock tree frequency for the C6 (fastest) speed grade CycloneIV device (as used on a DE2 board) is listed as 500MHz. So it will be quite a challenge for you to do that.
Altera_Forum
Honored Contributor I
42 Views

That's not the only tricky part. The other tricky part going along with that one is the clock stability. Will the clock, 1,000,000 clocks later, be the 2ms you want at all times? Perhaps 2ms might wander between a delay of 0,999,900 and 1,000,100. If you want to keep the actual delay exact, then you'll need to be careful about what external source provides you with your clock. 

 

Dan