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Hi All,
What's the recommended flow for using the Design Assistant? Does it worth to enable it running automatically during each flow run or probably better execute it manually after the flow has already been completed?
Is running the Design Assistant automatically time-consumed task? How much could it increase the compilation time?
What rules of the Design Assistant are critical and should be ALWAYS checked?
How could I know what Design Assistant rules should I check?
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Hello,
Here are some useful references for you:
https://www.intel.com/content/www/us/en/products/docs/programmable/fpga-design-assistant-video.html
As far as I know it is not heavily time consuming during compilation.
As for which design rules you should always check, it depends on which part of the project you want to focus on, and what you have. For example if you are working on timing closure, you should check design rules under CLK and TMC categories, FLP could be helpful too. https://www.intel.com/content/www/us/en/docs/programmable/683082/21-3/design-assistant-rule-categories.html
If you are at the beginning of the project design phase, I'd suggest you start out by enabling the LNT and RES categories. Feel free to go through the design rules in the settings. As you go along you will know what you need to check.
Does this answer your question?
Regards,
Nurina
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Hello,
We do not receive any response from you on the previous answer provided. Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.
p/s: If any answer from community or Intel support are helpful, please feel free to mark as solution, give Kudos and rate 4/5 survey
Regards,
Nurina
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