Design Assistant

Altera_Forum · ‎06-11-2013

Hi, i have a question to the Quartus II Design Assistant.

In my design there is a reset synchronisation like this:

"async_res_in_n" is the asynchrounous external reset pin of my board and "sync_res_out_n" feeds all other registers in my designs.

This is what the Design Assistant wants to see.

But i always got the Warning Message:

Rule R102: External reset signals should be synchronized using two cascaded registers. Found 1 node(s) related to this rule.

Any idea ?

Altera_Forum · ‎06-12-2013

Have the same warning in my current design. On a reset signal that is syncronized with two cascaded registers.

You probably can ignore it (Disable rule/Suppress).

Altera_Forum · ‎06-14-2013

Thank you, I think the same