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Design Assistant

Altera_Forum
Honored Contributor II
‎06-11-2013 07:58 AM
1,431 Views

Hi, i have a question to the Quartus II Design Assistant. 

 

In my design there is a reset synchronisation like this: 

 

 

https://www.alteraforum.com/forum/attachment.php?attachmentid=7363  

 

 

"async_res_in_n" is the asynchrounous external reset pin of my board and "sync_res_out_n" feeds all other registers in my designs. 

 

This is what the Design Assistant wants to see. 

 

But i always got the Warning Message: 

 

Rule R102: External reset signals should be synchronized using two cascaded registers. Found 1 node(s) related to this rule. 

 

Any idea ?
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Altera_Forum
Honored Contributor II
‎06-12-2013 08:20 AM
671 Views

Have the same warning in my current design. On a reset signal that is syncronized with two cascaded registers. 

You probably can ignore it (Disable rule/Suppress).
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Altera_Forum
Honored Contributor II
‎06-14-2013 03:55 PM
671 Views

Thank you, I think the same

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