Design Compilation Error in quartus prime

[Sruthy]

Hi,

I am beginner to quartus prime. I am facing an error as shown below:

ID:21358 Verilog HDL error at <location>: '<string>' is not a port

but the port is already declared as input

Error(21358): Verilog HDL error at d_ip_i3c_mipi_syn.v(398): 'scan_no_rst_alt' is not a port

input [3:0] scan_no_rst_alt

how to resolve this?

[sstrell]

Without seeing more code, there's really no way to figure out what is going on.

[RichardTanSY_Altera]

Without looking at the code, it is hard to debug what might cause the error.

Please share the design file or project (Project > Archive Project) that could duplicate the error.

Regards,

Richard Tan

[RichardTanSY_Altera]

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