Design compilation not possible with newer version of Quartus Prime

[bit42]

A few years ago I managed to completely implement the HACK computer of the From-Nand-To-Tetris project on a Terasic DE0-CV FPGA board (with VGA screen and PS2 keyboard). The design compiled without any problems with Quartus Lite version 17.0.0. Now I've tried compiling with version 23.1.1 and I get an error message: "Error (276003): Cannot convert all sets of registers into RAM megafunctions when creating nodes ..." Can this error be resolved by adjusting the compilation settings in the new version?

[bit42]

Here's more information: Before the compilation with Quartus 23.1.1 quits the following messages are shown: "Info (276014): Found 1 instances of uninferred RAM logic" and "Info (276007): RAM logic "memory:i_memory|ram16k:i_ram16k|ram_s" is uninferred due to asynchronous read logic".

The VHDL code that causes these messages is the following:

entity ram16k is
port (
   clk : in std_logic;
   i : in std_logic_vector(15 downto 0);
   load : in std_logic;
   address : in std_logic_vector(13 downto 0);
   o : out std_logic_vector(15 downto 0)
);
end ram16k;

architecture behavior of ram16k is

   type ram_t is array(0 to 16383) of std_logic_vector(15 downto 0);
   signal ram_s : ram_t := (others =>(others => '0'));
begin
   o <= ram_s(to_integer(unsigned(address)));
   process (clk)
   begin
      if (falling_edge(clk) and load = '1') then
      ram_s(to_integer(unsigned(address))) <= i;
      end if;
   end process;
end behavior;

The RAM of the "From Nand-To-Tetris"-system has such an asynchronous read.  Quartus 17.0.0. inferred this with the message "276020 Inferred RAM node ... from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design".

Is there a way to configure Quartus 23.1.1, to do this in the same way?

[RichardTanSY_Intel]

The error message indicate that ::

CAUSE: You specified a set of registers in a Verilog Design File (.v) or VHDL Design File (.vhd) that act as RAM. However, Analysis & Synthesis cannot implement the registers as RAM hardware because the read logic for the RAM is not fully synchronous.

ACTION: If you do not want Analysis & Synthesis to implement the register logic with RAM hardware, no action is required. If you want Analysis & Synthesis to implement the register logic with RAM hardware, ensure that either the read address or the output of the RAM are registered.

You may also checkout the KDB below:

https://www.intel.com/content/www/us/en/support/programmable/articles/000086642.html

• The read address is registered but has a preserve attribute attached to it.
• The read address is registered but has a fast_input_register assignment and is implemented as an IO register.

Above scenarios will also cause the RAM to be uninferred.

Regards,

Richard Tan

[RichardTanSY_Intel]

Any update on this?

Do you able to resolve the issue?

Regards,

Richard Tan

[RichardTanSY_Intel]

We noticed that we haven't received a response from you regarding the latest previous question/reply/answer, and will now transitioning your inquiry to our community support. We apologize for any inconvenience this may cause and we appreciate your understanding.

If you have any further questions or concerns, please don't hesitate to reach out. Please login to https://supporttickets.intel.com/s/?language=en_US, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.

The community users will be able to help you on your follow-up questions.

Thank you for reaching out to us!

Best Regards,

Richard Tan

[bit42]

Sorry for my late reply, I was sick. Unfortunately I haven't been able to solve the problem yet. When I use a solution with synchronous reading, the machine code programs no longer run. But they do that with Quartus Prime Lite version 17.0.0. I need to look into this in more detail. Thank you very much for your answers so far.