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Design compilation not possible with newer version of Quartus Prime

bit42
Beginner
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A few years ago I managed to completely implement the HACK computer of the From-Nand-To-Tetris project on a Terasic DE0-CV FPGA board (with VGA screen and PS2 keyboard). The design compiled without any problems with Quartus Lite version 17.0.0. Now I've tried compiling with version 23.1.1 and I get an error message: "Error (276003): Cannot convert all sets of registers into RAM megafunctions when creating nodes ..." Can this error be resolved by adjusting the compilation settings in the new version?

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bit42
Beginner
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Here's more information: Before the compilation with Quartus 23.1.1 quits the following messages are shown: "Info (276014): Found 1 instances of uninferred RAM logic" and "Info (276007): RAM logic "memory:i_memory|ram16k:i_ram16k|ram_s" is uninferred due to asynchronous read logic".

The VHDL code that causes these messages is the following:

entity ram16k is
port (
   clk : in std_logic;
   i : in std_logic_vector(15 downto 0);
   load : in std_logic;
   address : in std_logic_vector(13 downto 0);
   o : out std_logic_vector(15 downto 0)
);
end ram16k;

architecture behavior of ram16k is

   type ram_t is array(0 to 16383) of std_logic_vector(15 downto 0);
   signal ram_s : ram_t := (others =>(others => '0'));
begin
   o <= ram_s(to_integer(unsigned(address)));
   process (clk)
   begin
      if (falling_edge(clk) and load = '1') then
      ram_s(to_integer(unsigned(address))) <= i;
      end if;
   end process;
end behavior;


The RAM of the "From Nand-To-Tetris"-system has such an asynchronous read. 
Quartus 17.0.0. inferred this with the message "276020 Inferred RAM node ... from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design".

Is there a way to configure Quartus 23.1.1, to do this in the same way?

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RichardTanSY_Intel
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The error message indicate that ::

CAUSE: You specified a set of registers in a Verilog Design File (.v) or VHDL Design File (.vhd) that act as RAM. However, Analysis & Synthesis cannot implement the registers as RAM hardware because the read logic for the RAM is not fully synchronous.


ACTION: If you do not want Analysis & Synthesis to implement the register logic with RAM hardware, no action is required. If you want Analysis & Synthesis to implement the register logic with RAM hardware, ensure that either the read address or the output of the RAM are registered.


You may also checkout the KDB below:

https://www.intel.com/content/www/us/en/support/programmable/articles/000086642.html

  • The read address is registered but has a preserve attribute attached to it.
  • The read address is registered but has a fast_input_register assignment and is implemented as an IO register.

Above scenarios will also cause the RAM to be uninferred.


Regards,

Richard Tan


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