- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
I tried to use dc with one of my designs and Altera's stratix ii gx library.
I specified constraints (clock, reset wires, false paths, etc), and got it to compile. However, timing is horrible (some points have 40ns delay - probably due to fanout, but I've had the design running with a 10 ns clock when synthesized with quartus), and it appears to use almost twice as much area as quartus's netlist (assuming the area reported by dc is in LUTs). Has anyone else had experience in using dc with quartus? Did you find similar issues? Do you need to optimize post-synthesis to acheive your timing closure? Thanks, baverLink Copied
3 Replies
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
--- Quote Start --- I tried to use dc with one of my designs and Altera's stratix ii gx library. I specified constraints (clock, reset wires, false paths, etc), and got it to compile. However, timing is horrible (some points have 40ns delay - probably due to fanout, but I've had the design running with a 10 ns clock when synthesized with quartus), and it appears to use almost twice as much area as quartus's netlist (assuming the area reported by dc is in LUTs). Has anyone else had experience in using dc with quartus? Did you find similar issues? Do you need to optimize post-synthesis to acheive your timing closure? Thanks, baver --- Quote End --- Hi, I'm not very familar with the Synopsys DesignCompiler, but why are using the DC? Is it a special version for FPGA's. If not, I would expect results like yours. If you use a synthesis tool , which is not aware of the special features (e.g. DSP blocks) and the routing structure you will get worse results.
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
I thought Synopsys ended all FPGA support with their Design Compiler/FPGA Compiler tools, and subsequently purchases Synplify. That being the case, I would completely avoid using those tools to target an FPGA.
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Ahh, well, that would explain the issue. Thanks all.
Reply
Topic Options
- Subscribe to RSS Feed
- Mark Topic as New
- Mark Topic as Read
- Float this Topic for Current User
- Bookmark
- Subscribe
- Printer Friendly Page