Device out of range. Compilation error after changing device assignment

[Altera_Forum]

Compilation error after changing the device assignment (and allowing the removal of all location assignments) from a Cyclone III EP3C10E144C8 to a Cyclone II EP2C35F672C6. This is a monstrously long one-line error message (I added red color for emphasis): 

 Error (12252): SPI_bridge_2: "Device" (device) (EP3C10E144C8) out of range. Valid ranges:   The error doesn't make sense because it's calling out the old device. I notice that old value EP3C10E144C8 lingers in these two files:  SPI_bridge_2.qsys (which was not modified by compilation)  <parameter name="device" value="EP3C10E144C8" />  SPI_bridge_2.sopcinfo (which was modified by compilation)  <parameter name="AUTO_DEVICE"> <type>java.lang.String</type> <value>EP3C10E144C8</value> <derived>false</derived> <enabled>true</enabled> <visible>false</visible> <valid>true</valid> </parameter>  It's as if I can't change the device. Should I start a new project when porting from Cyclone III to Cyclone II?

[Altera_Forum]

You need to modify the settings in your Qsys project (as well as any Megafunction IP you might have) to target the new device. Changing the setting in Quartus does not propogate down.

[Altera_Forum]

Thanks Ted, that did the trick! All I had to do was open and save: Tools | Qsys | filename.qsys | Open | File | Save. 

 I neglected to mention the other five error messages (or is it only three), which I hoped would go away when the device ID was correct but did not. Hoping you have some guidance with these too:  Error (12252): Port object altpll_avalon|altpll inst sd1|clk of width 5 is being assigned the port altpll_avalon|altpll inst sd1|stratixii_pll inst pll7|clk of width 3 which is illegal, as port widths dont match nor are multiples. CAUSE : The port widths are mismatched in the mentioned assignment. The port widths of the connected ports should match or the LHS port width should be a multiple of the RHS port width. ACTION : Check the port widths of the connected ports. Logical operation results in a porERROR Error (12252): Port object altpll_avalon|altpll inst sd1|clk of width 5 is being assigned the port altpll_avalon|altpll inst sd1|stratixii_pll inst pll7|clk of width 3 which is illegal, as port widths dont match nor are multiples. CAUSE : The port widths are mismatched in the mentioned assignment. The port widths of the connected ports should match or the LHS port width should be a multiple of the RHS port width. ACTION : Check the port widths of the connected ports. Logical operation results in a porERROR Error (12153): Can't elaborate top-level user hierarchy Error: Quartus II 64-Bit Analysis & Synthesis was unsuccessful. 3 errors, 24 warnings Error: Peak virtual memory: 507 megabytes Error: Processing ended: Sun May 04 20:25:23 2014 Error: Elapsed time: 00:01:07 Error: Total CPU time (on all processors): 00:00:54 Error (293001): Quartus II Full Compilation was unsuccessful. 5 errors, 24 warnings

[Altera_Forum]

Sounds like you have an ALTPLL megafunction (or component added within Qsys) that also needs to be updated.

[Altera_Forum]

You did say update the IP. That did the trick, thanks Ted. For posterity the procedure was, 

• double-click on filename.qsys in the Project Navigator 
• In Qsys, System Contents tab, double click on the megafunction (my case Avalon ALTPLL) 
• In the MegaWizard Plug-In Manager, change the currently selected device family (my case from Cyclone III to Cyclone II), after unchecking "Match project/default" which by the way appears to be derelict  
• Finsh, Save, Compile