Difference of 2 process?

Altera_Forum · ‎11-29-2013

I have a VHDL code for process as below:

   process (vin_clk)   begin
      if rising_edge(vin_clk) then
         if (rst_n = '0') then
            data_cnt <= "000000000000";
         elsif (frame_flag_vin = '1') then
            data_cnt <= "000000000000";
         elsif (vin_de = '1') then
            if (data_cnt = vin_width - "000000000001") then
               data_cnt <= "000000000000";
            else
               data_cnt <= data_cnt + "000000000001";
            end if;
         else
            data_cnt <= data_cnt;
         end if;
      end if;
   end process;

My question is: if to delete the last "else" branch (data_cnt <= data_cnt;), what will the difference be? or no difference?

Altera_Forum · ‎11-29-2013

It's the same. See the RTL view.

Altera_Forum · ‎11-29-2013

No difference, because all signals hold their value in VHDL anyway.

If you did it without a clock, it would also make no difference, as either way (with or without the else) you would be inferring a latch.

It is usual to leave out anything that occurs implicitly (like the final else branches).

What you're asking in the code is for the synthesisor to connect the en port of the inferred register to everything in the if branches.