Different external memories on same bus

[KS019]

Hi,

In the existing design, I have SRAM, SDRAM, NVRAM, EEPROM on a same parallel bus which is managed by a Microprocessor. But know I want to migrate to ARRIA10 FPGA with Nios II processor. With SRAM and SDRAM IPs available in quartus tool, I get two different buses for two memories. I need to get a single bus to control all the memories present in my existing design. 

Can anyone suggest how can  do this.

Regards,

Kumar

[hareesh]

Hi,

Could pls share your existing design screenshot or .qsys file?

[hareesh]

Hi,

Any update ?

[hareesh]

As we do not receive any response from you on the previous question/reply/answer that we have provided. Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.

[hareesh]

Hi,

can you pls share existing platform design ?

[hareesh]

which ip's are using for SRAM and SDRAM interfacing?

pls respond

[hareesh]

Hi,

in bellow page you can find out all details of external memory ip support details

https://www.intel.com/content/www/us/en/support/programmable/support-resources/support-centers/emif-support.html#introtext_1660180280

Thanks,

[hareesh]

i think you got solution and sine long you are not responding.

As we do not receive any response from you on the previous question/reply/answer that we have provided. Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.