Different phases in PLL

[Altera_Forum]

Hi everyone, 

 I've a problem with the alt_pll megafunction and I can't find any solution why is that... I want to use PLL as a simple reconfigurable clock distribution but at first I wanted to check how it works. I created the simplest PLL with normal mode in wizard. There are 5 outputs but what amazed me all of them are not in phase... I tried other modes but it still doesn't work. Any suggestions why is that ? Below I give a link to the page with pictures of it... http://www.pdi.republika.pl/ (http://www.pdi.republika.pl/) . Thanks for any help...

[Altera_Forum]

What device? What pins are the outputs on? In some devices there are dedicated PLL outputs, while other outputs are just regular I/O, and there may be some variation between those. Look at the Tco timing report, right-click and do a Report Timing. This way you can analyze the timing paths in more detail, rather than looking at a simulation.

[Altera_Forum]

I've tried to do it on Cyclone III devices with Quartus II ver. 7.2, but the results are exactly the same... but as You wrote the problem is probably in pin assigments as I thought too. I'll try to find in documentation what pins are exactly for PLL.... because till now I did it without changing pins... just the graphical schematic then compilation and simulation... I'll write how it works :) Thanks for help 

  ---------------------------------------------------------------------------------------------  .... I set the pins manually without trusting the automatic fitter and it's much better. Of course this is just the simulation but better simulation = better working in real .. :)

[Altera_Forum]

according to the pictures, there are some ps between the clock, whcih apperas to me very realistic. Where exactely is the problem ?

[Altera_Forum]

If you are interested in finding out the clock distribution delay, you should avoid taking the PLL clock outputs straight to pin as that may introduce unrelated routing delay. 

 You can try the following circuit:  Have a TFF feed DFF then drive out to an output pin. Use each clock output of PLL to feed each set of TFF and DFF. TCO of this circuit will be the sum of input clock delay + PLL offset + PLL clock tree to IO cell delay + IO cell output register to pin delay.  BTW, you need enable fast output register on DFF so that they go into IO cell. You may also have to enable other options to make sure DFF doesn't get synthesized away.  In order to get relevant comparison, you should make sure your output pins are adjacent to each other and in the same IO bank. You should also note that the clock delay to IO cell register may be different than that of a core register.