Good morning,
I've designed a system whose the critical part is composed basically by a RAM and a FIFO. I read from the RAM the number of the data which have to be extracted from the FIFO. For example, if in the RAM - address X - there is the number "5", five data will be extracted from the FIFO. I have written a state machine which controls the operations. Fortunately, every new output must be different from the output before. Thus my FSM states are: 1) set the read request to one; 2) wait for the extraction of one data; 3) If the data is extracted (then, when the new data is different from the old data) close the read request and redo the process while the number of data extracted is minor of the number recorded in the RAM. Until the data is not out, the state of the FSM doesn't change. I've used an Altera 64bit 4K word DCFIFO and an altera true dual port RAM, but for now input and output are clocked with the same oscillator (50 MHz). The figure in attachment shows the behavior of the program. My question is why the extraction of some data from the FIFO takes twice the time of the others. Sometime a data is out after 280 ns, sometime after 140 ns... Is there a simple reason? I have to look for the problem in the FIFO or in the FSM? I would that the data extraction takes always the same time. thanking in advance I greet you all. Dario
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OK, this is my code:
when s4 => if(wrclk'event and wrclk ='1') then numberoftimestamp <= q_b; -- RAM output send_state <=S5; end if; when s5 => if(wrclk'event and wrclk ='1') then if wrempty ='0' then if unsigned(numberoftimestamp) >000000 and forlooper < unsigned(numberoftimestamp) then rdreq<='1'; send_state <= S6; else forlooper<="000000"; send_state <=S8; end if; else send_state <=s7; end if; end if; when S6 => if(wrclk'event and wrclk ='1') then if q /= MACinput then rdreq<='0'; forlooper <=forlooper +1; send_state <= S7; else send_state <=S6; end if; end if; when S7 => if(wrclk'event and wrclk ='1') then MACinput<=q; send_state <= S5; end if; when S8... The address of the RAM in incremented and the FSM state reset. MACinput is the signal that I want always at the same time. I'm a beginner about the VHDL programming, so I apologize for stupid mistakes :)Take a book, read about VHDL basics. Remember, we are talking here about description, not programming language.
Read this, do the changes according example and try again: http://quartushelp.altera.com/13.0/mergedprojects/hdl/vhdl/vhdl_pro_state_machines.htm