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15308 Discussions

Differential DQS MAX10 assignment using DIY altddio_bidir.

BrianHG
New Contributor I
508 Views

Hello,  I'm trying to custom drive the DQS pins on a MAX10 FPGA setting their IO standard to all the possible compatible differential IO standards, driving the IO using the altddio_bidir.

 

Here is the error I get:

Error (176202): The differential I/O standard Differential 1.5-V SSTL cannot be used on the pin DDR3_DQS_p[0], because the specified pin uses a tri-stated output buffer.

Same if I use LVDS_E_3R.

I had no problem with the 'DDR3_CK' differential since it is an output only, but, the DQS needs to be bidirectional.

 

I can fake it by feeding the altddio_bidir an N&P signal and run the pins in single ended mode, however, when receiving data, the DQS will loose the precision gained by having a differential input buffer.

 

How can I work around this?

Altera's ALTDQS does a few things behind a hidden door, not to mention some weird timing setup and phase delay not under my strict .sdc control.  I have yet to try it as I want the entire DDR bus to appear common where I control the my own PLL's read/write/dqs clocks.

Also, wouldn't specifying the DQS pins into differential still generate the same fitter error?

 

I'm using a MAX10 and using the official DQS & DQS(n) IO pins.

 

0 Kudos
7 Replies
BrianHG
New Contributor I
502 Views

I've attempted the 'dummy' software cross feeding a 1 and 0 to the data in H & L of the altddio_bidir to generate 2 outputs, a p&n IO pad.  I now get this new error instead:

Error (169008): Can't turn on open-drain option for differential I/O pin DDR3_DQS_n[0]

I am not sure if this is any closer, but at least the DDR3_DQS_p[0] pins are still labeled as differential and they made it through.

 

Oops, the IO wasn't assigned.  I still get the same tri-state error.

 

BrianHG
New Contributor I
466 Views

Ok, I tried using 'altiobuf_bidir' which has both differential and bidirectional capability, yet Quartus says:

Error (176202): The differential I/O standard Differential 1.5-V SSTL cannot be used on the pin DDR3_DQS_p[0], because the specified pin uses a tri-stated output buffer.

 

Even worse, I cannot simulate in ModelSim when using the 'altiobuf_bidir'.  It is not a recognized function.

 

It would seem Altera's Mem-phy seems to access the DQS pins as bidirectional differential I/O standard Differential 1.5-V SSTL fine, but I am at a loss as how to do so directly.

 

Now I know I can use something like altdq_dqs2, however, it is not compatible with Cyclone IV/III, or others.  Their older altdqs doesn't support differential and wont work on newer cyclones and max 10 fpgas.

 

yoichiK_intel
Employee
458 Views

Hi

Which version of Quartus software are you using to implement altddio_bidir with MAX10 device ?

As far as I see I do not find the altddio_bidir in IP Catalog when I set the device as MAX10.

BrianHG
New Contributor I
450 Views

Quartus 15 and 20.1.

You are correct that it does not show up in the IP catalog if you look.

But if you have it in your existing code, how are you supposed to know?

It gets worse as it does function completely in simulation, both RTL and Gate level.

It also funchtions in hardware when in input mode.  It's when your coded switches it to output that the IO is output, but dead.  But the simulation says it's working and Quartus does not complain at all.

All these little Quartus bugs waste weeks of debugging time.

I have switched it to 'altera_gpio_lite' which has fixed the output and differential DQS functionality.  Now I have a new problem.  Using 'altera_gpio_lite', ModelSim gives me an entire stream (like 20x) of:

** Warning: (vsim-3722) altera_gpio_lite.sv(908): [TFMPC] - Missing connection for port 'nsleep'.
# ** Warning: (vsim-2685) [TFMPC] - Too few port connections for 'ibuf'. Expected 4, found 3.

 

And Quartus Prime 20.1 give these warnings:

Warning (10036): Verilog HDL or VHDL warning at altera_gpio_lite.sv(82): object "nsleep_in" assigned a value but never read

How do I fix this?  I'm not even calling 'ibuf', it's what was generated by your IP Megafunction library.

When I call the 'altera_gpio_lite', I do have:

.nsleep ({16{1'b0}});.....

 

My code should be clean, free of these warnings.

 

yoichiK_intel
Employee
439 Views

Hi

When I see the GPIO Lite IP opening with MAX10 device the GUI shows the nsleep is not available in selected device.  I assume if you leave the port open the Quartus will not generate any warnings or you can safely ignore the warning messages.

 

BrianHG
New Contributor I
432 Views

Leaving the port open was the first thing I tried.  The error still appears.  In fact, it was the GUI which generated that ' .nsleep ({16{1'b0}}) '.

 

ModelSim error with the line included:

# ** Warning: (vsim-2685) [TFMPC] - Too few port connections for 'ibuf'. Expected 4, found 3.
# Time: 0 ps Iteration: 0 Instance: /BrianHG_DDR3_PHY_SEQ_tb/DUT_PHY_SEQ/genblk7/BHG_DDR3_IO_PORT_ALTERA/genblk1/DDR3_IO_DQS/gpio_one_bit/i_loop[0]/altgpio_bit_i/genblk5/diff_input_buf/diff_input_buf_without_nsleep/ibuf File: altera_gpio_lite.sv Line: 879
# ** Warning: (vsim-3722) altera_gpio_lite.sv(879): [TFMPC] - Missing connection for port 'nsleep'.

 

(Remember, I do not call ibuf.)  New additional errors on top of the original with the port omitted:

# ** Warning: (vsim-2685) [TFMPC] - Too few port connections for 'DDR3_IO_CK'. Expected 22, found 21.
# Time: 0 ps Iteration: 0 Instance: /BrianHG_DDR3_PHY_SEQ_tb/DUT_PHY_SEQ/genblk7/BHG_DDR3_IO_PORT_ALTERA/genblk1/DDR3_IO_CK File: BrianHG_DDR3_IO_PORT_ALTERA.sv Line: 200
# ** Warning: (vsim-3722) BrianHG_DDR3_IO_PORT_ALTERA.sv(200): [TFMPC] - Missing connection for port 'nsleep'.

 

With nothing but a void in the port's brackets, I still get the same original warnings...

 

BrianHG
New Contributor I
430 Views

I trying to make clean code which doesn't generate pages of warnings.  There is no reason why my code using 'altddio_in/out/bidir' has 0 errors or warnings while the 'altera_gpio_lite.sv' generates a full page (yes 67 lines  worth of warnings) messing up the console where I have important messages mixed in.

If it was 1 warning, or 4 for the 4 times I call the port, it wouldn't be too bad.  But how can I post example code and explain to those using my code to learn that the problems isn't my coding style, but you will need to question Intel why their tools have this huge list of warnings which you should ignore only when using MAX 10 fpga?

 

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