I have a verilog design which contains an array and for all intents and purposes, I am not allowed to modify the source. I compile it in Quartus II v11.0 and it infers a RAM (M9K to be exact). That inference is causing a timing issue/logic issue and I would like to prevent Quartus from inferring a RAM for this module only.
I am well aware of the ramstyle = "logic" directive I could add to the verilog, but that is not an option which leads me to my question:
Can you disable the inference of a RAM for a given module (will be applied to all instances of the module) in the QSF file?
