Divided integer number

[Altera_Forum]

Can I divide the integer number (for example, 120) to each of the numbers 1 2 0 in different variables?

[Altera_Forum]

What exactly is the context? What are you trying to do? 

You could extract 1 2 0 out in VHDL - but why?

[Altera_Forum]

From the AD converter to read 8-bit vector and the need to get him on the numbers in an integer. I need to send individual characters to UART

[Altera_Forum]

--- Quote Start ---  From the AD converter to read 8-bit vector and the need to get him on the numbers in an integer. I need to send individual characters to UART  --- Quote End ---    Problem solved. This is example.  library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all;   entity test is port( INput:in integer range 0 to 999:=123);   end test;   architecture main of test is signal hundred:integer range 0 to 9;  signal ten :integer range 0 to 9 ;  signal unit : integer range 0 to 9;    begin  hundred<=INput/100; --1 ten<=((INput rem 100)/(10)); --2 unit<=(INput rem 10) ; --3 end main;

[Altera_Forum]

Hello please.  

 I need to show 12 -bit value (integer) of the AD converter to the 4 - digit display.   This is my functional code, but takes 756 total logic elements (many).  I need a way to effectively divide the number and use the minimum number of logic elements.  library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all;   entity Number_converter is port( INPUT12bit: in unsigned (11 downto 0); digit1: out unsigned (11 downto 0); digit2: out unsigned (11 downto 0); digit3: out unsigned (11 downto 0); digit4: out unsigned (11 downto 0)); end entity;   architecture main of Number_converter is signal INPUT12bit_INT:integer range 0 to 4096; attribute ramstyle: string; attribute ramstyle of digit4 : signal is "M9K"; begin   digit1<=(INPUT12bit rem 10)/1; digit2<=(INPUT12bit rem 100)/10; digit3<=(INPUT12bit rem 1000)/100; digit4<=(INPUT12bit/1000);   end main;

[Altera_Forum]

I can't read VHDL, sorry. But if you want to trade logic elements for hard memory blocks you could use a look-up table. It would need to be 2^12 deep (4096) and wide enough to drive your 4-digit display. I would think this would take 4 bits per digit, but you've got your output digits defined as 12 bits each. Assuming you only need 16 bits out (4 bits per digit) the look-up table would consume 8 M9Ks I believe. They're there so you may as well use them.

[Altera_Forum]

Why don't you simply use the standard function to_string() ?  

This way, each number can be addressed by indexes representing each descending decimal order.

[Altera_Forum]

--- Quote Start ---  Why don't you simply use the standard function to_string() ?  This way, each number can be addressed by indexes representing each descending decimal order.  --- Quote End ---    Because to_string is not synthesisable.  To the op.. Why not just have it in hex? That way you just need a small lut for each hex digit.

[Altera_Forum]

If you don't need it fast, you can use a double dabble algorithm, which cqn help you convert binary to the base of your choice, even bcd.

[Altera_Forum]

--- Quote Start ---  If you don't need it fast, you can use a double dabble algorithm, which cqn help you convert binary to the base of your choice, even bcd.  --- Quote End ---    Please, How to?

[Altera_Forum]

use your favorite web search engine an enter double dabble as keywords, you'll find plenty of resources there.

[Altera_Forum]

--- Quote Start ---  use your favorite web search engine an enter double dabble as keywords, you'll find plenty of resources there.  --- Quote End ---    Problem solved. This is my code. 133 logic elements  library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all;   entity converter is port( INPUT12bit: in unsigned (11 downto 0):="000000101010";  digit1_out: buffer integer range 0 to 10;  digit2_out: buffer integer range 0 to 10;  digit3_out: buffer integer range 0 to 10;  digit4_out: buffer integer range 0 to 10;  clk :in std_logic); end entity;   architecture main of converter is   begin     process(clk) variable digit1: integer range 0 to 10; variable digit2: integer range 0 to 10; variable digit3: integer range 0 to 10; variable digit4: integer range 0 to 10; VARIABLE decount_INPUT12bit :unsigned (11 downto 0); variable default_INPUT12bit :unsigned (11 downto 0); variable LAST_INPUT12bit :unsigned (11 downto 0); variable LAST1_INPUT12bit :unsigned (11 downto 0); variable ENABLE: std_logic:='0';   begin       if rising_edge(clk) then      if ENABLE='1' then  decount_INPUT12bit := decount_INPUT12bit - 1;  digit1:=digit1 + 1;  if digit1=10 then  digit1:=0;  digit2:=digit2 + 1;  if digit2=10 then  digit2:=0;  digit3:=digit3 + 1;  if digit3=10 then  digit3:=0;  digit4:=digit4 + 1;  end if;  end if;  end if;  end if;    if LAST_INPUT12bit/=INPUT12bit then  ENABLE:='1';  if INPUT12bit/=LAST1_INPUT12bit then  decount_INPUT12bit:=INPUT12bit;  default_INPUT12bit:=INPUT12bit;  LAST1_INPUT12bit:=INPUT12bit;    digit1:=0;  digit2:=0;  digit3:=0;  digit4:=0;  end if;  end if;      if decount_INPUT12bit = "000000000000" then  LAST_INPUT12bit:=default_INPUT12bit;  ENABLE:='0';  digit1_out<=digit1;  digit2_out<=digit2;  digit3_out<=digit3;  digit4_out<=digit4;  end if; end if;   end process; end main;

[Altera_Forum]

This might have a small logic footprint, but I can see the performance being rather poor, due to the large cascaded logic chains because of no pipelining.

[Altera_Forum]

--- Quote Start ---  This might have a small logic footprint, but I can see the performance being rather poor, due to the large cascaded logic chains because of no pipelining.  --- Quote End ---    Yes I need little logic elements. Slow transfer no harm. This module will be multiplexed for 8 digits - 4digit and 4 digit

[Altera_Forum]

Could you use code tags when posting code in the future? 

This makes it way esier to read.