Does Max 10 need "derive_pll_clocks" in constraint file

[KeyEng]

Below is from "Quartus® Prime Pro Edition User Guide":

Note: Only Arria 10 and Cyclone® 10 GX devices support the Derive PLL Clocks
(derive_pll_clocks) constraint. For all other supported devices, the Timing
Analyzer automatically derives PLL clocks from constraints bound to the related IP. 

Appreciate if any one can confirm that for MAX 10 series we do not need to have "derive_pll_clocks" in the constraint file according to above statement in the user guide.

[Kenny_Tan]

Only Stratix 10, Agilex 7, and Agilex 5 devices do not require derive_pll_clocks in the .sdc file. For all other Intel FPGA devices, including MAX 10, the use of derive_pll_clocks is required unless PLL-generated clocks are explicitly constrained using create_generated_clock.

[FvM]

Don't refer to Quartus Pro user guide for devices only supported by Quartus Standard.

[Kenny_Tan]

Not sure if you have further question? If no, we shall close the thread.

[Kenny_Tan]

As we do not receive any response from you on the previous answer that we have provided. Please login to ‘https://supporttickets.intel.com/s/?language=en_US’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.