I am synthesizing Systemverilog RTL which has export construct in it and is not supported by Synplify. I wonder if any one has faced this issue and what workaround can be used.
Does Quartus support export construct from Systemverilog?
May I know which edition of the software you are using?
According to https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/po/ss-quartus-comparison.pdf, the Intel Quartus Prime Standard/Lite edition software have limited SystemVerilog language support.
May I know what export you are referring to? Could you provide an example? Besides this, you can check the SystemVerilog synthesis support for Pro edition software in https://www.intel.com/content/www/us/en/programmable/quartushelp/current/index.htm#hdl/vlog/vlog_list_sys_vlog.htm.
I am actually getting error in Synplify tool as it does not support export. I have not tried the code in Quartus yet. Below is the export of package which is present in RTL.
I did check SystemVerilog synthesis support page of Quartus and it does not mention export.
I am using Quartus Prime Pro 18.1 and want to know if export is supported by Quartus.