Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
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Doesn't generate CXL testbench for example design

Dangranla
Beginner
274 Views

Hi,
  As I follow the《Agilex™ 7 R-Tile Compute Express Link* (CXL*) 1.1/2.0 FPGA IP Design Example User Guide》generate the example desing.

  Trying to simulate the testbench withe VCS or Questsim, but the CXL testbench file doesn't generated in the path said in user guide 4.3.1
  I've already ticked the simulation and PIPE options while generating the example design.

  

  os: windows

  quartus prime pro 24.3

 

regards,

Wang

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4 Replies
RongYuan
Employee
206 Views

Hi,

Please make sure you have an IP license.

https://www.intel.com/content/www/us/en/products/details/fpga/intellectual-property/interface-protocols/cxl-ip.html#tab-blade-1-0


You can create an empty project based on AGIB027R29A1E1VB. Find CXL IP in IP Catalog then make sure "Simulation" is selected before clicking "Generate Example Design".


In the generated Type 2 example design of my test case, there is a cxl_ed_tb directory containing a tb.zip.



Regards,

Rong



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Dangranla
Beginner
194 Views

Hi Rong,
  I've confirmed that I've got the license and "Simulatuion" is selected 

Dangranla_0-1744811318843.png

 
 

Dangranla_0-1744811454398.png

there are not cxl_ed_tb file in neither hardware_test_desing nor intel_rtile_cxl_top_cxltyp2_ed

Dangranla_2-1744811630357.png

Dangranla_3-1744811641838.png

 

 

 

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RongYuan
Employee
150 Views

Please try all English in project path, both your base project and the created one.


Regards,

Rong


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Dangranla
Beginner
111 Views

Both of my project and created one are English path

Regards,

Wang

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