Avalon Clock Crossing Bridge with write response support

[FabianL]

Hello,

we would require a Avalon Clock Crossing Bridge with support for the Avalon Write Response & Write Response Valid signals.

However the Avalon Clock Crossing Bridge does not show any options to enable those signals and also does not provide the interface if the respective Host/Agents have one:

Is there any possibility to add support for write reponse signals to the Clock crossing Bridge?

best regards

Fabian

[ShengN_Intel]

Hi Fabian,

Avalon Clock Crossing Bridge didn't use the write response and write response valid signals.

Btw, you may refer to the waitrequest (low) and write signals (low) for complete transaction. Check this link https://www.intel.com/content/www/us/en/docs/programmable/683091/22-3/memory-mapped-interface-signal-roles.html

A write command is considered accepted when the last beat of the burst is issued to the agent and waitrequest is low.

Thanks,

Regards,

Sheng

[FabianL]

Thanks for the hint, but that gives me only the completion of the Avalon write transaction to the Clock Crossing Bridge, but not to the final target.

But if you have a multi master scenario this cannot be used to tell, when data actually is written to the target.

E.g. the following scenario:

In this case the DMA controller cannot know when the Clock crossing bridge actually completes the transfer due to the variable delay of its internal FIFO. Thus it may happen, that the Interrupt to the NIOS arrives too early and the data is not yet written to the external memory.

It depends on the overall load on the shared EMIF Avalon MM Interface and the fillstate of the FIFO in the clock crossing bridge.

The risk that this happens may be reduced by reducing the size of the clock crossing bridge FIFO and by adding additional wait cycles before issuing the ISR, but so far I have not found a reliable way to guarantee a coherent execution order.

Any suggestions on this scenario?

best regards

Fabian

[ShengN_Intel · Accepted solution]

Hi Fabian,

If so, I would suggest you to use Clock crossing adapter type handshake check this link https://www.intel.com/content/www/us/en/docs/programmable/683609/24-1/interconnect-parameters-59023.html to enforce that each write must fully complete before the next is accepted

Thanks,

Regards,

Sheng

[FabianL]

Hi Sheng,

thanks for the hint to this option.

best regards

Fabian

[ShengN_Intel]

Hi Fabian,

Let me know if you have any further concern or consideration?

Thanks,

Regards,

Sheng