Doesn't generate CXL testbench for example design

[Dangranla]

Hi,
  As I follow the《Agilex™ 7 R-Tile Compute Express Link* (CXL*) 1.1/2.0 FPGA IP Design Example User Guide》generate the example desing.

  Trying to simulate the testbench withe VCS or Questsim, but the CXL testbench file doesn't generated in the path said in user guide 4.3.1
  I've already ticked the simulation and PIPE options while generating the example design.

  os: windows

  quartus prime pro 24.3

regards,

Wang

[RongYuan]

Hi,

Please make sure you have an IP license.

https://www.intel.com/content/www/us/en/products/details/fpga/intellectual-property/interface-protocols/cxl-ip.html#tab-blade-1-0

You can create an empty project based on AGIB027R29A1E1VB. Find CXL IP in IP Catalog then make sure "Simulation" is selected before clicking "Generate Example Design".

In the generated Type 2 example design of my test case, there is a cxl_ed_tb directory containing a tb.zip.

Regards,

Rong

[Dangranla]

Hi Rong，
  I've confirmed that I've got the license and "Simulatuion" is selected 

there are not cxl_ed_tb file in neither hardware_test_desing nor intel_rtile_cxl_top_cxltyp2_ed

[RongYuan]

Please try all English in project path, both your base project and the created one.

Regards,

Rong

[Dangranla]

Both of my project and created one are English path

Regards,

Wang

[RongYuan]

Hi,

Please check if Questa tool is installed and EDA Tool Settings has Questa selected.

Regards,

Rong