Simulating Virtual JTAG IP Core

[allenS1]

Hi ,

I'm using Quartus version 22.1std

I want to simulate the Virtual JTAG IP Core, and I've already inputted several simulation stimuli that I'd like to test in the IP Parameter Editor:

From here, what do I need to do so that I can see the IP core processing these stimuli? I've tried instantiating the IP in a testbench module and moving time forward to see if something happens, but I don't see any thing happening:

In the EDA section of the Parameter Editor, it's supposed to show any simulation model files that are needed to simulate the design, but this list is empty:

Any help in figuring this out would be appreciated.

Thanks.

[ShengN_Intel]

Hi,

You may check the design example in this document https://cdrdv2-public.intel.com/666577/ug_virtualjtag-683705-666577.pdf (page 27). Attached the modified code, waveform for your reference.

Thanks,

Regards,

Sheng

[ShengN_Intel]

Hi,

May I know if you have any further update or concern?

Thanks,

Regards,

Sheng