Duty cycle VHDL

[Altera_Forum]

Hello! 

 I'm trying to create an A and B pulse and change the duty cycle of that pulse. The program shown below just changes the frequency and creates an A and B pulse, but I'm not able to change the duty cycle.  Has anyone a tip or idea??  library ieee; use ieee.std_logic_1164.all;  entity freq is    port(   clk :in std_logic;   rst :in std_logic;   S0 :in std_logic;  out_0 :out std_logic;   out_1 :out std_logic  );   end freq;   architecture Behavioral of freq is    signal cnt : integer;   signal temp : std_logic;   signal temp_out : std_logic;    begin   --XXXXXXXXXXXXXXXXXXXXXXXXXXXX --CLOCK  process(clk)   begin   if(rst='1') then   temp <= '0';   cnt <= 0;   elsif(clk'event and clk='1') then   if(cnt= 1000000) then   temp <= not temp;  cnt <= 0;   else   cnt <= cnt +1 ;   end if;   end if;    --XXXXXXXXXXXXXXXXXXXXXXXXXXXX --Switch   if (S0='1') then  temp_out <= temp;    else   temp_out <= '0';    end if;    end process;   out_0 <= temp_out;   out_1 <= not temp_out;   end Behavioral;

[Altera_Forum]

Hi Frans 

Infact your code simply creates a 50/50 square wave. I think this is what you need:  library altera; library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; -- for the unsigned type entity pwm_generator is port (CLKIN : in std_logic; TPERIOD : in unsigned(7 downto 0); TWIDTH : in unsigned(7 downto 0); PWM : out std_logic ); end entity pwm_generator; architecture pwm_gen_a of pwm_generator is subtype small_int is natural range 0 to 500; begin update: process(CLKIN) is variable tcnt : small_int := 0; begin if rising_edge(CLKIN) then tcnt := tcnt + 1; if tcnt = TPERIOD then tcnt := 0; end if; if tcnt >= TWIDTH then PWM <= '0'; else PWM <= '1'; end if; end if; end process; end architecture pwm_gen_a;  You may need to change TPERIOD and TWIDTH bit length to meet your specs. You must also add the pwm switching function.