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quartus ii 64-bit version 13.0.0 build 156 04/24/2013 sj full version:
I got the following message, if I want to generate the netlist of my design: Info: Command: quartus_eda --read_settings_files=on --write_settings_files=off .... bla bla Warning (11101): Unable to generate the VHDL EDA simulation netlist files because the Quartus II software does not currently support VHDL post-compilation simulation for the Cyclone V devices. How can I generate pre and post netlists (VHDL) of my design? For other devices, e.g. cyclone IVE works.Link Copied
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seems pretty clear that VHDL models aren't yet supported for Cyclone V

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