PLL Configuration problem on ModelSim 6.6d

Altera_Forum · ‎09-30-2013

Hello,

I’m currently working on a project where I have to use a PLL. After having done the configuration and the compilation on Quartus II 12.1sp1 Web Edition, I then run a simulation (gate level) on ModelSim-Altera 6.6d. But after a few minutes, during the simulation the general clock (frequency: 100MHz) and the PLL clock stops. I don’t know why. In the transcript window I get the following message:

**Note: Cyclone III PLL locked to incoming clock

Time: 48354 ps Iteration: 0 Instance: /batch_3_cycl3/\PLL_dynam|altpll_component|autogenerated|plll|

**Warning: */DFFEAS Hold High VIOLATION ON DATAIN WITH RESPECT TO CLK;

Expected := 0.212 ns; Observed := 0.121 ns; At: 17565.647 ns

In my project I use a Cyclone III FPGA.

Can someone please help me with this problem?

Thanks

Altera_Forum · ‎10-14-2013

To be more specific the goal of my project is to do 48 measurements in a wire, but during the simulation of the software when it gets to these 48 measurements, all the clocks stops suddenly.

This is the screenshot of the RTL simulation (which works fine):

file:///C:/DOCUME~1/viale/LOCALS~1/Temp/msohtmlclip1/01/clip_image001.png

But in the GTL simulation I get this:

file:///C:/DOCUME~1/viale/LOCALS~1/Temp/msohtmlclip1/01/clip_image003.png

I don’t know if it’s a problem in the software or a problem of configuration in Quartus II.