Solved: EMIF link project error in Quartus 18.0

jkhoo · ‎11-01-2023

I am encountering error while running EMIF toolkit on quartus 18.1. the error are as follow:

Prior to running this, i selected option-1 in the diagnostics tab of DDR3 SRAM Controller with Uniphy Intel FPGA IP. How can i fix this issue?

initialize_connections
Preparing to create a connection to System Console. This may take several seconds.
A connection to System Console was successfully established on port 57289
link_project_to_device -device_name {5SGXEA3K(1|2|3)|5SGXMA3K1|..@1#USB-1} -hardware_name {USB-BlasterII on localhost (USB-1)} -sof_file {C:\intelFPGA\proj\RFV5_C0016v1_LB_emif\output_files\Rapidfire_v5.sof}
Linking device 5SGXEA3K(1|2|3)|5SGXMA3K1|..@1#USB-1 on hardware USB-BlasterII on localhost (USB-1) using .sof file C:/intelFPGA/proj/RFV5_C0016v1_LB_emif/output_files/Rapidfire_v5.sof.
Error occurred while running the System Console command design_link {/designs/Rapidfire_v5.sof} {/devices/5SGXEA3K(1|2|3)|5SGXMA3K1|..@1#USB-1}. System Console returned the result java.util.concurrent.ExecutionException: java.lang.Exception: design_link: Device /devices/5SGXEA3K(1|2|3)|5SGXMA3K1|..@1#USB-1 is not compatible with design /designs/Rapidfire_v5.sof (Device has usercode 04EA1EE6 but design has usercode FFFFFFFF)
invoked from within
"design_link /designs/Rapidfire_v5.sof /devices/5SGXEA3K(1|2|3)|5SGXMA3K1|..@1#USB-1
"
invoked from within
"interp eval $slave {
design_link /designs/Rapidfire_v5.sof /devices/5SGXEA3K(1|2|3)|5SGXMA3K1|..@1#USB-1

}". You must shutdown the toolkit and restart.
ERROR: An error occurred while linking the project to the device.

jkhoo · ‎11-13-2023

Hi Adzim,

Error message (0x80070005) was resolved by enabling JTAG server apps to communicate through "Private" and "Public" profile in Windows Defender Firewall.

After resolving this Error message (0x80070005), I still face the same issue of executing:

"{C:/intelfpga/18.1/quartus//../nios2eds/Nios II Command Shell.bat} make all 2>> stderr.txt"

I eventually figure out that Quartus Prime 18.1 std can't work with wsl (windows subsystem for linux).

(The reason i enabled wsl in the first place was because i have both Quartus P 18.1 std and 22.1 in the same PC. And Quartus P 22.1 need WSL to compile ddr3 ip.)

So i resolved the ddr3 IP compilation by unchecking Windows Subsystem for Linus in Windows Features.

4 fix ddr3 IP failed generation by disabling windows subsystem for linux .png

View solution in original post

AdzimZM_Intel · ‎11-03-2023

Hello,

The error messages indicate that your design has different device with the board.

Can you verify if the design is using same device as the board?

Regards,

Adzim

jkhoo · ‎11-05-2023

Hi Adzim,

I just verified and the device is the same.

I also saw another failure when generating the DDR IP.

below is the error i am encountering:

<html>Info: "MyDDR3_master" instantiated altera_mem_if_ddr3_phy_core "p0"
<html>Info: "MyDDR3_master" instantiated altera_mem_if_ddr3_afi_mux "m0"
Error: Error during execution of "{C:/intelfpga/18.1/quartus//../nios2eds/Nios II Command Shell.bat} make all 2>> stderr.txt": child process exited abnormally
Error: Execution of command "{C:/intelfpga/18.1/quartus//../nios2eds/Nios II Command Shell.bat} make all 2>> stderr.txt" failed
Error: Authorized application C:\intelFPGA\18.1\quartus\bin64\jtagserver.exe is disabled in the firewall.
Error: Add failed: 0x80070005
Error: WindowsFirewallAddApp failed: 0x80070005
Error: ]2;Altera Nios II EDS 18.1 [gcc4]C:/intelfpga/18.1/quartus//bin64/uniphy_mcc -ac_code sequencer_mc/ac_rom.s -inst_code sequencer_mc/inst_rom.s -ac_rom ../MyDDR3_master_s0_AC_ROM.hex -inst_rom ../MyDDR3_master_s0_inst_ROM.hex -header sequencer/sequencer_auto.h -vheader ../sequencer_auto_h.sv -ac_rom_init sequencer/sequencer_auto_ac_init.c -inst_rom_init sequencer/sequencer_auto_inst_init.c -DAC_ROM_USER_ADD_0=0_0000_0000_0000 -DAC_ROM_USER_ADD_1=0_0000_0000_1000 -DAC_ROM_MR0=0100001000001 -DAC_ROM_MR0_CALIB= -DAC_ROM_MR0_DLL_RESET=0100101000000 -DAC_ROM_MR1=0000000000100 -DAC_ROM_MR1_OCD_ENABLE= -DAC_ROM_MR2=0001001011000 -DAC_ROM_MR3=0000000000000 -DAC_ROM_MR0_MIRR=0100000100001 -DAC_ROM_MR0_DLL_RESET_MIRR=0100010100000 -DAC_ROM_MR1_MIRR=0000000000100 -DAC_ROM_MR2_MIRR=0001000111000 -DAC_ROM_MR3_MIRR=0000000000000 -DQUARTER_RATE=0 -DHALF_RATE=1 -DFULL_RATE=0 -DNON_DES_CAL=0 -DAP_MODE=0 -DGUARANTEED_READ_BRINGUP_TEST=0 -DMEM_ADDR_WIDTH=13 -DHARD_PHY=0

AdzimZM_Intel · ‎11-08-2023

Hi,

Is the issue still exist at your end?

From the error messages, it's seem the issue is related to firewall.

Firewall setting can interfere with JTAG server.

Can you please check with your admin once.

We don't have any setting to tell Platform Designer to leave the firewall alone.

Regards,

Adzim

jkhoo · ‎11-13-2023

Hi Adzim,

Error message (0x80070005) was resolved by enabling JTAG server apps to communicate through "Private" and "Public" profile in Windows Defender Firewall.

After resolving this Error message (0x80070005), I still face the same issue of executing:

"{C:/intelfpga/18.1/quartus//../nios2eds/Nios II Command Shell.bat} make all 2>> stderr.txt"

I eventually figure out that Quartus Prime 18.1 std can't work with wsl (windows subsystem for linux).

(The reason i enabled wsl in the first place was because i have both Quartus P 18.1 std and 22.1 in the same PC. And Quartus P 22.1 need WSL to compile ddr3 ip.)

So i resolved the ddr3 IP compilation by unchecking Windows Subsystem for Linus in Windows Features.

4 fix ddr3 IP failed generation by disabling windows subsystem for linux .png

AdzimZM_Intel · ‎11-16-2023

I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.

EMIF link project error in Quartus 18.0

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