Early timing analysis + Intel's IP

[matferronato]

Hello,

I updated Quartus Prime Pro to version 23.4, which gives me access to the Early Timing Analysis using RTL-on-SDC files.

The majorities of my clocks are defined by the sdc files automatically created by the Multi Channel DMA and PLL IPs.

When running the synthesis flow up to the Early Timing Analysis check, I see the PLL clock being sourced from the PLL IP files, but I don't see the PCIe application clock from the Multi Channel DMA files.

How can I add the PCIe clock to be used during Early Timing Analysis?

I tried to manually create the clock using the sdc command below

create_clock -name pcie_clk -period 2.000 -waveform {0 1} [get_pins {pcie_sys_inst|intel_pcie_ptile_mcdma_0|ast_hip|intel_pcie_ptile_ast_hip|inst|inst|maib_and_tile|hdpldadapt_rx_chnl_15|pld_pcs_rx_clk_out1_dcm}] -add

but it doesnt seem to work, quartus seems to ignore this line while loading the sdc file during synthesis.

Thanks for your help!

[TingJiangT_Intel]

Hi there, please try to check this with timing analyzer after compilation to see if it has the same issue.

[matferronato]

Hi TingJiang, thanks for the answer.

My problem happens during early timing analysis following the dni flow on quartus 23. Can you please explain your suggestion a little further?

Timing analyzer currently does not fetch the correct clocks from the ips sdc files. I cannot see the pcie clock being loaded.

[TingJiangT_Intel]

Sure, I want to confirm if the issue won't occur after full compilation with all IPs added to the project (After Fitter and Router Finishing) to locate if the issue is caused by early timing or other issues.

[matferronato]

Hi TingJiang, I see, know I understand your question better.

Yes, when I run a full compilation I see all the expected clocks both in the compilation reports and in the Timing Analyzer.

The problem only seems to appear in the dni flow, on the early timing analysis step.

[TingJiangT_Intel]

I see, can you upload a demo with the same issue, so I can try to reproduce and locate the problem.

[TingJiangT_Intel]

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