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Valued Contributor III
986 Views

Editing Altera IP Core

Hello there,  

 

I am using the altera avalon spi IP which I got from the IP Catalog in the Qsys window. The name in the catalog is "SPI (3 Wire Serial)". So far, it worked fine with my DE1-SoC. 

 

Because this IP does not support SPI in burst mode, I wanted to add this feature. So I changed the verilog code from the spi module (named something like soc_system_spi_0.v). The problem is that when I press "Generate HDL..." in the Qsys window, it overwrites my changes.  

 

What am I doing wrong? Should I make my changes in an other file? Or what is the easiest way to edit the Altera IP? 

 

I also tried to make a new component with the changed verilog code, but then the Avalon interface did not seem to be correct. 

 

Thanks in advance! 

 

By the way: the module is configured as SPI slave. 

 

frif
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Valued Contributor III
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A new component is the way to do this. As soon as the IP cannot be configured as you need then it becomes necessary to change the behaviour of your system or design your own IP. 

 

Yes, you can base your IP on the existing code. Qsys also offers templates within which you should write your IP. This generally ensures the Avalon-slave interface knits into Qsys correctly. Using one of those templates along with either your modified code or your own, should result in a custom IP module that Qsys can work with. 

 

Cheers, 

Alex
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Valued Contributor III
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Thanks for your help. I changed the code and created a custom IP module. It works now :)

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