Is there a way to resize the text boxes used for the ports? If not, is there a way to change the justification? For some reason when I create symbols from my HDL, the port names do not line up and take an exessive amount of space, especially if it is a bus port.
Any suggestions? I design in verilog but I like to have my top-level as a block diagram for documentation purposes.
The block diagrams are so messed up, they are difficult to read. Does anyone have suggestions on how to "clean-up" the diagrams?
