Dear all
there is a megawizard core -PLL in my design, and as i do simulation with modelsim, i did compiled altera's simulation library 22omodel.v as well as altera_mf.v to the simulation project . i gave the input signal clock to pll's inclk0, but there's no signal on pll's output c0 appears, (the c0 should have been a clk output), but when i download my design onto my developkit, i found the pll works well by watching signaltap
i called FIFO in my design ,then do simulation ,compiled simulation library as well. but as i said above, the FIFO does't behave proprely , when it is full, the wrfull signal was not driven up, and no output
thanks for your help:confused:
