Hello,
I am having a problem editing Altera megafunctions. I have a working piece of logic containing among other things an LVDS receiver, and wanted to edit the receiver to add an a_reset input and a pll_locked output. I edited the megafunction (MF) by right-clicking on the lvds component in the "Hierarchy" view and selecting the "megawizard plugin manager". After adding the two ports to the MF and clicking Finish twice, and modifying the main module to connect to those ports, my design ran into timing simulation trouble, namely setup violations of around -2.5 ns from the lvds receiver output to a fifo right after.
I changed everything back to the way it was, again by using the megawizard plugin manager and commenting out the two port references from the instantiation in the main module. However, the timing analyzer still shows the setup violations even though they were not there before I started modifying the LVDS MF..
I'm guessing I may be editing megafunctions the wrong way in general, or perhaps I am not doing a 'clean' compilation every time and some old (bad) settings are retained? Any help or comment is most welcome.
Some background: using Quartus 13.1.0 64-bit on Windows 7, programming a Stratix IV EP4SGX70HF35C2.
Cheers,
Daaf
