process inside another process?

[Altera_Forum]

Can there be a process inside another process ? 

 I want to put a process inside a for loop. so since the for loop cannot be written outside a process, i weanted to put the for loop also in one process. What can be the alternative solution for this ?  my code:  library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.numeric_std.all; entity ber is  port ( clk : in std_logic  );   end ber;   architecture ar of ber is   type data is array (0 to 11) of std_ulogic; signal d: data; -- give the input data bit by bit  signal q:std_logic_vector(0 to 3):="0001"; --signal rxd_bit:std_logic_vector(0 to 3):="1010"; -- shd be received from the txr signal k:std_logic_vector(0 to 3):="0000"; signal j,t: std_ulogic:='0';     begin    p1: process(j)  variable count : integer := -1;     begin      for j in 0 to 3 loop  p2: process(t) -----------> ERROR : Illegal sequential statements  variable m: integer := 0;   begin  m:=m+1;   exit when m=5;  q<=(q(2)xor q(3)) &q(0)&q(1)&q(2);   k<=q;     for t in 0 to 3 loop  if (k(t) /= d(t+(4*(j-1)))) then   count := count+1;   end if;  end loop;   end process p2;     end loop ;  end process p2; end ar;

[Altera_Forum]

Woooh !  

 1) I think you can't make a process inside a process  2) rename the loop variable 'j' and 't' OR rename/delete your SIGNALS 'j' and 't' : to avoid confusion  3) Could you post your schema ?  I bet you need a synchronous design, if so, employ   process(clk) -- or process(reset_n, clk) if you had a reset_n if rising_edge (clk) then q<=(q(2)xor q(3)) &q(0)&q(1)&q(2); k<=q; -- something like that : nested loops -- you must build finite loops because the FPGA have a finite number of logic elements AND synthesizer wouldn't want infinite structure. for j in 0 to 3 loop for t in 0 to 3 loop if (k(t) /= d(t+(4*(j-1)))) then count := count+1; end if; end loop; end loop; end if; end process; -- It could be written easier, maybe.

[Altera_Forum]

Processes are never ending loops, so it wouldnt make sense to make a never ending loop inside another never ending loop. 

 Why not just the code in the inner process in the outer process?

[Altera_Forum]

okk..The value of the signals will change only once the process ends. But i want the q and k value to change each timew it enters the j for loop..this is the code that needs to be modified so that k and q values are updated each time it enters the loop. 

 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.numeric_std.all; entity ber is  port ( clk : in std_logic  );   end ber;   architecture ar of ber is   type data is array (0 to 11) of std_ulogic; signal d: data; -- give the input data bit by bit  signal q:std_logic_vector(0 to 3):="0001"; signal k:std_logic_vector(0 to 3):="0000"; signal t: std_logic:='0';   begin        p2: process(clk)  variable count : integer := -1;   begin   if rising_edge(clk) then  for j in 0 to 2 loop  q<=(q(2)xor q(3)) &q(0)&q(1)&q(2); -- LFSR  k<=q;  end if;     for t in 0 to 3 loop  if (k(t) /= d(t+(4*j))) then   count := count+1;   end if;  end loop;     end loop;  end process p2; end ar;

[Altera_Forum]

Think about the logic you're trying to describe. Your j loop just does the same thing 3 times (it doesnt do anything different on each iteration) and the t loop adds between 0 and 4 to the count variable. 

 I think you need to start again. Before writing any code, draw the circuit you are trying to achieve on a peice of paper. VHDL is a description language, not a programming language. If you dont know the circuit, how do you expect to describe it?

[Altera_Forum]

the t loop works fine in comparing the bits in d array with the k value and count is incremented when they differ. 

 The j loop does the same work 3 times. yes.It is because the signal values change only at the end of the process.I want the q and k values to change every time it enters j loop. How do I do that?   I am sorry , I am new to VHDL .

[Altera_Forum]

You need to start again and rethink. This is NOT how to write VHDL. VHDL is NOT a programming language. It describes hardware.

[Altera_Forum]

You should refer to a good VHDL textbook or VHDL tutorial.

[Altera_Forum]

What is the purpose/goal of your "design" ? If it is not confidential. A checksum control on received bits ? 

What is the desired behaviour ?  The comparison "(k(t) /= d(t+(4*(j-1))))" sounds wrong, because for example t=0 and j=0 it gives d(-4) which doesn't exist. I guess 'd' may be a buffer whose size should be 4* size of 't'.    --- Quote Start ---  VHDL is NOT a programming language. It describes hardware.   --- Quote End ---  

[Altera_Forum]

--- Quote Start ---  What is the purpose/goal of your "design" ? If it is not confidential. A checksum control on received bits ? What is the desired behaviour ?  The comparison "(k(t) /= d(t+(4*(j-1))))" sounds wrong, because for example t=0 and j=0 it gives d(-4) which doesn't exist. I guess 'd' may be a buffer whose size should be 4* size of 't'.  --- Quote End ---     the purpose is to design a BER Tester. And when t=0 and j=0 it will be d(0)

[Altera_Forum]

--- Quote Start ---  the purpose is to design a BER Tester. And when t=0 and j=0 it will be d(0)  --- Quote End ---    sry yes. the code had glitches.