Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
Announcements
FPGA community forums and blogs on community.intel.com are migrating to the new Altera Community and are read-only. For urgent support needs during this transition, please visit the FPGA Design Resources page or contact an Altera Authorized Distributor.
17267 Discussions

Effect of Virtual Pins on Resource Utilization Statistic

Altera_Forum
Honored Contributor II
‎09-10-2015 06:55 PM
1,198 Views

Is the LUT used to implement a Virtual Pin included in the "Total Logic Elements" statistic found in the *.fit.summary file?  

 

In other words, is the following equation true (using stats from *.fit.summary): 

 

(Logic Utilization Without Virtual Pins) = (Total logic elements) - (Total virtual Pins) 

 

Thanks.  

 

 

PS: I'm using Quartus 13.0.
0 Kudos

Link Copied

1 Reply
Altera_Forum
Honored Contributor II
‎09-11-2015 12:22 AM
499 Views

Yes, it is included. 

In the fit report ".fit.rpt" there is a line describing virtual pins utilization in ALMs. See attached screenshot. 

Also, in the Resource Utilization By Entity section of the .fit.rpt there is a column telling how many of the resources are virtual pins. 

 

Thanks, 

Evgeni
Preview file
84 KB
0 Kudos
Copy link
Reply

Community support is provided Monday to Friday. Other contact methods are available here.

Intel does not verify all solutions, including but not limited to any file transfers that may appear in this community. Accordingly, Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade.

For more complete information about compiler optimizations, see our Optimization Notice.