Community
cancel
Showing results for 
Search instead for 
Did you mean: 
Altera_Forum
Honored Contributor I
1,268 Views

Embedded JAM byte-code player failure with Quartus 17

Hi all 

 

I implemented the Jam STAPL ByteCode Player (revision 2.2) on an embedded platform in order to program/configure a MAX10 FPGA via JTAG directly from an embedded processor. 

 

This was working well and the sequence of events to update the MAX 10 was: 

- Compile new FPGA image in Quartus v15 or v16. 

- Convert *.pof to *.jbc using Quartus Programmer. 

- Compile *.jbc data as part of embedded software image. 

- Run embedded application, which then updates the FPGA via the JTAG port. 

 

With Quartus v17 I find that the embedded JAM byte-code Player fails with an exit code 10: JBIC_INTERNAL_ERROR. 

 

What I have found is the following: 

- The v17 *.jbc (generated from the *.pof) triggers a "configuring SRAM device(s)..." step which was not seen during programming before. 

- On inspecting the *.jam format for quartus v16 and v17 I saw that the "ALG_VERSION" has incremented from 67 to 68. (JAM version remains 2.0) 

- I can compile my FPGA image with Quartus v17 and then use the quartus_cpf.exe utility from Quartus 16 to generate the *.jbc and achieve success. (Hence I assume algorithm 67 or 68 is used within the quartus_cpf.exe utility...) 

 

My questions: 

- What changed between JAM generation algorithm 67 and 68 and why?  

- Is this a known issue that the embedded STAPL bytecode player is unable to program pof jbc files generated with algorithm 68? (or is this an issue with my implementation of the jbc player) 

 

I can obviously use the workaround as described, but would appreciate any more information on this to ensure that I do not run into incompatibilities in the future.
0 Kudos
3 Replies
Altera_Forum
Honored Contributor I
46 Views

Did you ever figure this out? 

 

I'm having a very similar problem, but the STAPL files built with Quartus 18. Works fine when created with Quartus 16, using the non-bytecode player 2.5. 

 

I also see the new "configuring SRAM" step. However, mine fails on "Exit code = 6... Unrecognized device", so the failure may be slightly different.
Altera_Forum
Honored Contributor I
46 Views

Hi 

 

No I was not able to achieve success with the tools as is... 

 

What I currently do is to compile my FPGA image in Quartus 17 and then I use the "quartus_cpf.exe" utility from the Quartus 16 install directory to generate the JBC format. (Instead of generating the .jbc from within Quartus 17) 

 

"Unrecognized device" does sound like it might be a different issue though, can you confirm that the device ID is being read correctly?
dbind2
Novice
46 Views

Hi,

I encountered the same problem.

I run most of the JBC PLAYER within a big microcontroller and only a very small number of functions on a separate microcontroller which serves the JTAG lines.

Programming jbc files which were generated with Version 16.1 (file converter) from within quartus ide works nicely.

Programming jbc files which were generated with Version 18.1 (file converter) from within quartus ide does not work.

Programming fails during "configuring SRAM device(s)..." step and this step is an additional step compared to Version 16.1.

 

I think I found a solution.

I run the quartus_cpf.exe not from the ide but from the command line.

With that the outputs for Version16.1 and Verision18.1 are identically.

The command I use is this: quartus_cpf.exe -c file.pof file.jbc

 

regards,

Dennis

 

 

Reply