Embedding build number in VHDL?

[Altera_Forum]

I'd like some automatic way of putting a build or release or version number into my design so that I can check what version a given PCB is programmed with. Can anyone suggest how to do this? 

 I've done this in 'C' by running a batch file as part of a build before doing the compile. The batch file generates a header file that I can# include and consists of a# define statement for the revision number.   My first proble is that I don't know how to add a pre-build operation in Quartus.   My second problem is that I don't know how to do a# include in VHDL. I guess I could write the whole VHDL in my batch file.

[Altera_Forum]

You have PRE_FLOW_SCRIPT_FILE and POST_FLOW_SCRIPT_FILE in Quartus, see examples in Quartus Software Handbook. Writing VHDL text (a package) in tcl seems to be the best way to place the information.

[Altera_Forum]

http://www.alteraforum.com/forum/showthread.php?t=1925&highlight=timestamp 

That one is verilog, but I believe others have done VHDL.

[Altera_Forum]

Use a generic or parameter in your top-level design, and then set the generic via a Tcl script; 

 # Build timestamp# - Tcl returns the same as set timestamp puts " - Build timestamp ($timestamp 0x)" # Generics set_parameter -name TIMESTAMP $timestamp Cheers, Dave

[Altera_Forum]

Thanks guys, the timestamp script looks to be my best way forward. I'd rather go with my Subversion revision number, but a timestamp is a reasonable substitute.

[Altera_Forum]

--- Quote Start ---  Thanks guys, the timestamp script looks to be my best way forward. I'd rather go with my Subversion revision number, but a timestamp is a reasonable substitute.  --- Quote End ---  In CVS you can use a tag in the Tcl, e.g., I think something like the following  set revision_string "$$Revision : $$"  which gets re-written during CVS checkin as  set revision_string "$$Revision : 1.23 $$"  After CVS checkin of the script, you could then parse the string to extract a version number, and then convert that into your register values. You could probably do the same for SVN too.  However, the pain with this approach is that specific file never really changes, so the string never updates.  I personally use a design version register with a value I manually update, and a build time register.  Cheers, Dave

[Altera_Forum]

It doesn't really work with SVN because the SVN revision number is the file's revision, not the tree's. So if you don't modify the tcl script itself, it will keep an old revision number. Most SVN installations have a utility that can be used to get the highest SVN revision number in a whole tree though, and it should be possible to call it from the tcl script.

[Altera_Forum]

My other suggestion is to write a script that places day, month, year, and version into RAM and then these RAM contents are read via USB/Serial interface. While many have suggested using TCL, my preference is to use Python and automatically generate the entire VHDL (or Verilog) code for this portion of the design.