I've started using Quartus Prime Pro (currently using 19.4) and have noticed that it does not output VHDL assert statements to the messages during compilation like Quartus Standard does. It also doesn't error when it hits an assert statement that evaluates to false with severity set to error. Is there a way to enable it to process assert statement in VHDL during compilation like it does in Standard?
We're using assert statement throughout our design to validate parameters and to provide messages that are used to verify the design is setup right when there are issues. This is a show stopper for us if we can't get this working.
ASSERT is not typically a synthesizable construct so I'm surprised this ever displayed anything during a compilation in Quartus standard. It's meant for simulation only.
I do see in Quartus help that there are messages that can be displayed for ASSERT, so it's possible that the move to Pro, with a synthesis engine that more closely follows the IEEE standards which say to ignore ASSERT during synthesis, that this feature was removed. Can you provide code example(s)? That might help to see if there's an equivalent to what you're trying to do.
We commonly using assert to do checks on parameters during synthesis:
entity SomeEntity is generic map ( DATA_WIDTH : natural ); port map ( data : std_logic_vector(DATA_WIDTH-1 downto 0) ); end entitiy; architecture arch of SomeEntity is begin assert DATA_WIDTH < 10 report "Data widths larger than 10 are not supported" severity error; end architecture;
We also use it to simple output a message about what was compiled for future reference.
entity SomeEntity is generic map ( CONFIG1 : complex_record_type ); port map ( -- some ports ); end entitiy; architecture arch of SomeEntity is function complex_enable_check(config: complex_record_type) return boolean is begin -- A complex function here that return a boolean based on a complex configuration record end function; begin assert false report "Config1 value1 is " & integer'image(CONFIG1.value1) severity note; assert false report "Config1 value2 is " & integer'image(CONFIG1.value2) severity note; genBlock: if complex_enable_check(CONFIG1 ) generate assert false report "<Design block name> is enabled" severity note; -- Design block here end generate; end architecture;
We use complex record types and function in many place in our design that enable different blocks of code and it's useful to be able to output their values and results during synthesis. This allows us to look back at the message outputs when we have problems to help figure out the problem. Some of the function we use are hundreds of line of VHDL and many of our configuration type are records with many layer of nested records and arrays, so it's often not easy to understand what is happening without assert statements.
Any suggestions you have for alternatives would be appreciated.