Encoding Type: User-Encoded

Altera_Forum · ‎02-26-2012

I set in Quartus "State Machine Processing: User-Encoded" and I set encoding in my Verilog source. I am using the latest version of the Quartus.

I do not understand why when I look in Analysis & Synthesis report I see different codes like below.

For example I set for st0 0010 and in the report is 0000.

Encoding Type:  User-Encoded
+---------------------------------------------------+
; State Machine - |fsm_kody|state                   ;
+-----------+---------+---------+---------+---------+
; Name      ; state~5 ; state~4 ; state~3 ; state~2 ;
+-----------+---------+---------+---------+---------+
; state.st0 ; 0       ; 0       ; 0       ; 0       ;
; state.st8 ; 0       ; 1       ; 1       ; 1       ;
; state.st1 ; 1       ; 0       ; 1       ; 0       ;
; state.st9 ; 1       ; 0       ; 1       ; 1       ;
; state.st4 ; 1       ; 0       ; 0       ; 0       ;
; state.st5 ; 1       ; 0       ; 0       ; 1       ;
; state.st2 ; 1       ; 1       ; 1       ; 0       ;
; state.st7 ; 1       ; 1       ; 1       ; 1       ;
; state.st3 ; 1       ; 1       ; 0       ; 0       ;
; state.st6 ; 1       ; 1       ; 0       ; 1       ;
+-----------+---------+---------+---------+---------+
      
      
      
+--------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: Top-level Entity: |fsm_kody ;
+----------------+-------+-------------------------------------------------+
; Parameter Name ; Value ; Type                                            ;
+----------------+-------+-------------------------------------------------+
; st0            ; 0010  ; Unsigned Binary                                 ;
; st1            ; 1000  ; Unsigned Binary                                 ;
; st2            ; 1100  ; Unsigned Binary                                 ;
; st3            ; 1110  ; Unsigned Binary                                 ;
; st4            ; 1010  ; Unsigned Binary                                 ;
; st5            ; 1011  ; Unsigned Binary                                 ;
; st6            ; 1111  ; Unsigned Binary                                 ;
; st7            ; 1101  ; Unsigned Binary                                 ;
; st8            ; 0101  ; Unsigned Binary                                 ;
; st9            ; 1001  ; Unsigned Binary                                 ;
+----------------+-------+-------------------------------------------------+

Altera_Forum · ‎02-26-2012

Quartus user manual:

"If necessary, the software inverts bits in a user-encoded state machine to

ensure that all bits of the reset state of the state machine are zero."

So then it is not user encoded! Is possible to turn off this inversion?

Altera_Forum · ‎02-27-2012

As long as you require an asynchronous reset, e.g. POR to initial state, the corresponding bit vector must be all zero. Registers initialzed to '1' are inverted during compilation. Refer to "NOT gate push-back" in the Quartus software handbook.

Thus the shown coding is at least necessary for the gate level representation of the state variable. What's your point of requiring a particular polarity for all state variable bits?

If the state variable is copied e.g. to a std_logic_vector, the respective bit may be possibly inverted. Did you try?

Altera_Forum · ‎02-27-2012

FvM,

thanks for your help. "NOT gate push-back" is good hint.

I am doing research on the impact of FSM encoding on power consumption so I need to set particular polarity for all state variable bits.

Altera_Forum · ‎02-27-2012

I see. But I would be surprized if register polariry affects power consumption. Of course, if you manage to force Quartus to insert an inverter level between the state register and the succeeding logic, power consumption will be affected. But I guess, Quartus tries it's best to ignore such attempts.