Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
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Equivalent of #pragma message in verilog

Altera_Forum
Honored Contributor II
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Hi, 

 

Is there an equivalent compiler directive which allows displaying user defined messages in Quartus like C++. I would like to display a warning or error messages during quartus compiles using verilog. 

 

Thanks.
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