Testbench in Modelsim problem: no signal clear in a loop

Altera_Forum · ‎05-05-2010

Hi,

I'm doing a project that writes text in a VGA. I'm doing the testbench to try everything, and i want to generate the rows and columns of my VGA with the testbench, i need it to know which pixel i have to write. I'm using a 640x480 resolution, so using a 25.175MHz clock, i have to generate 800 columns and 528 rows. But this isn't the problem...

The problem is when i try to generate those rows and columns, with two for loops, the signal column doesn't clear, .... The Fila (row) signal increases every 800 Columna(column) but Columna doesn't clear, so it grows till 1023(10bits) and overflows, so changes to 0.

any suggestion?


signal Clck : std_logic :='0';
	constant PERIOD1 : time := 60 ns;
--Clock generation:
		gen_clock : process(Clck)	
			begin
				Clck <= not Clck after PERIOD1/2;
		end process;
--Row & Column generation for the system				
		gen_col_row : process
		   	begin
					nReset<='0';	
					wait for PERIOD1;
					nReset<='1';
					
					Columna<=(others=>'0');	--Initialize counters 
					Fila<=(others=>'0');	
					
					wait until ((Clck'event) AND (Clck='1'));	--Clock synchronization
					
					for i in 1 to 528 loop	--Generates Fila(Row)
						for j in 1 to 800 loop	--Generates Columna(Column)
							Columna<=Columna+'1';--Columna = column in spanish...
							
							wait for PERIOD1;
							
						end loop;
						
						Columna<=(others=>'0'); --THIS DOESN'T WORK!!!!!!
						Fila<=Fila+'1';--Fila=Row in spanish....
					end loop;
		end process;

Thank you very much!

Sergi.

Altera_Forum · ‎05-05-2010

My Comments next to your code


--Clock generation:
        gen_clock : process(Clck)    
            begin
                Clck <= not Clck after PERIOD1/2;
        end process;

This does not need to be in a process. It works fine as a line outside.


--Row & Column generation for the system                
        gen_col_row : process
               begin
                    nReset<='0';    
                    wait for PERIOD1;
                    nReset<='1';
                    
                    Columna<=(others=>'0');    --Initialize counters 
                    Fila<=(others=>'0');    
                    
                    wait until ((Clck'event) AND (Clck='1'));    --Clock synchronization
                    
                    for i in 1 to 528 loop    --Generates Fila(Row)
                        for j in 1 to 800 loop    --Generates Columna(Column)
                            Columna<=Columna+'1';--Columna = column in spanish...
                            
                            wait for PERIOD1;
                            
                        end loop;
                        
                        Columna<=(others=>'0'); --THIS DOESN'T WORK!!!!!!
                        Fila<=Fila+'1';--Fila=Row in spanish....
                    end loop;
        end process;

You need to wait after Fila <= Fila + 1; otherwise it goes straight back into the next loop, and with no wait, the column <= '0' is overridden with the column <= column + 1;

To fix this either:

1. after fila <= fila + 1; put wait for 0ns; (this causes the simulator to skip 1 delta cycle, and will set columna to 0;

2. Use variables instead of signals for row and column instead. They are updated immediatly and you wont have this problem.

Altera_Forum · ‎05-05-2010

Thank you very much for your response, now, is working!!!!

Is there any advantage of not using a proces for the clock generation? And, any advantatge of using variables instead of signals and the wait?

Thank you!!!

Altera_Forum · ‎05-06-2010

For clock generation: Not really. Its just extra code that's not needed. If you have a more complicated clock scheme (like having the ability to turn it on and off to speed up simulation) you will need it inside a process.

As for variables: they require much less memory than signals. But be careful you understand how they work.

Altera_Forum · ‎05-06-2010

Thank you!