Error 10028, 10029 Verilog

Altera_Forum · ‎04-23-2013

I'm having a problem with Error 10028 and Error 10029 when i try and compile this in Quartus. I am using Quartus 2 Verilog HDL program language. I also receive this error but I'm hoping when what I'm doing wrong is fixed it will go away...

quartus 2 internal error

Internal Error: Sub-system: VRFX, File: /quartus/synth/vrfx/vrfx_sgate.cpp, Line: 1785

oterm == clk

Stack Trace:

0x190c: thr_thread_var_get + 0xc (ccl_thr)

End-trace

Quartus II Version 9.1 Build 350 03/24/2010 SJ Web Edition

Service Pack Installed: 2

These are two separate always (AT) statements, There is more code telling what should happen when each of these states occur but I'll leave that out for now. I just don't quiet understand why I'm getting the errors I'm getting. The only coding background I have is a college level Java class as well as a little Verilog coding exercises.

But here are the errors I am receiving when I put in the following code:

errors

Error (10028): Can't resolve multiple constant drivers for net "state.AA" at controller2.v(60)

Error (10029): Constant driver at controller2.v(35)

Error (10028): Can't resolve multiple constant drivers for net "state.AB" at controller2.v(60)

Error (10028): Can't resolve multiple constant drivers for net "state.AC" at controller2.v(60)

Error (10028): Can't resolve multiple constant drivers for net "state.AD" at controller2.v(60)

Error (10028): Can't resolve multiple constant drivers for net "state.AE" at controller2.v(60)

Error (10028): Can't resolve multiple constant drivers for net "state.AF" at controller2.v(60)

Error (10028): Can't resolve multiple constant drivers for net "state.AG" at controller2.v(60)

Error (10028): Can't resolve multiple constant drivers for net "state.AH" at controller2.v(60)

Error (10028): Can't resolve multiple constant drivers for net "state.AI" at controller2.v(60)

Error (10028): Can't resolve multiple constant drivers for net "state.AJ" at controller2.v(60)

Error (10028): Can't resolve multiple constant drivers for net "state.A" at controller2.v(60)

Error (10028): Can't resolve multiple constant drivers for net "state.B" at controller2.v(60)

Error (10028): Can't resolve multiple constant drivers for net "state.C" at controller2.v(60)

Error (10028): Can't resolve multiple constant drivers for net "state.D" at controller2.v(60)

Error (10028): Can't resolve multiple constant drivers for net "state.E" at controller2.v(60)

Error (10028): Can't resolve multiple constant drivers for net "state.F" at controller2.v(60)

Error (10028): Can't resolve multiple constant drivers for net "state.G" at controller2.v(60)

Error (10028): Can't resolve multiple constant drivers for net "state.H" at controller2.v(60)

Line 35 is the always (AT) (posedge enter) statement

Line 60 is the always (AT) (posedge clk) statement

code


/*
*    Always (AT) statement that when the user presses enter, will change from 1 state to the next until it hits state "A",
*    this continues on later. Cycle from states (AA to AJ) each time a certain pushbutton (enter) is pressed. Once all states have
*    been cycled through, go to the start of the next set of states (A).
*    
*    input: enter, pushbutton using debouncer
*    input: state, AA - AJ and A - N
*/
always (AT) (posedge enter) begin
    
    case (state)
    
        AA: state <= AB;            
        AB: state <= AC;
        AC: state <= AD;
        AD: state <= AE;
        AE: state <= AF;
        AF: state <= AG;
        AG: state <= AH;
        AH: state <= AI;
        AI: state <= AJ;
        AJ: state <= A;
    endcase
end
/*
*    Always (AT) statement that cycles between desired states (A - N) after initial states have passed (AA - AJ).
*    
*    input: clk, clock signal
*/
always (AT) (posedge clk) begin
    case (state)
        
        A: state <= B;
        B: state <= C;
        C: state <= D;
        D: state <= E;
        E: state <= F;
        F: state <= G;
        G: state <= H;
        H: state <= I;
        I: state <= J;
        J: state <= K;
        K: state <= L;
        L: state <= M;
        M: state <= N;
        N: state <= A;
        
    endcase
end

code description

The way it works in my head is: It stays at state "AA" until I press enter, when I do it changes to the next state. Once it hits state "A" it uses a clock signal to begin the loop needed to change between stats. Any help with this would be appreciated. When I edit out each section the file compiles fine but when they are both there together I get this issue.

PS: (AT) is actually the AT sign, but this forums syntax doesnt allow new people to post links and I guess it see's any AT sign as a link...

Altera_Forum · ‎04-24-2013

you cannot assign state in multiple always blocks.

Altera_Forum · ‎04-24-2013

You would have to combine those into a single case statement.

The reason why you can't make assignments to 'state' using multiple case statements is because they operate concurrently. Java code like you are used to would just execute those case statements sequentially but that's not how hardware languages describe the behavior.

An analogy would be you have a highway with a single lane called "state" and you are trying to jam two cars down this highway that are side by side (the two case statements).

Altera_Forum · ‎04-26-2013

Thank you, yeah that makes sense. My big problem is trying to change between the first set of states to the second set of states.

At the moment, I'm thinking of breaking the 2 separate triggers into a single trigger before I ever hit that module so I don't get that error. I'll be using a clock signal that changes every second and a pushbutton that goes when I tell it to. I need to input 10 numbers into the other code so I want the pushbutton to have priority for the first 10 cycles, then the clock can take over.

I've created a separate module to accommodate this but now I don't understand why my outputs are always stuck at VCC.

The code below should:

Take 2 inputs, when sw_in is triggered my count variable will go up by one and it will output the sw_in to sw_out. Once count reaches 2'd10 it will let clk_out become clk_in.


module counter(clk_in,sw_in,clk_out,sw_out);
input clk_in,sw_in;
output reg clk_out,sw_out;
reg  count;
initial begin
count = 2'd00;
end // end initial
always (AT) (posedge sw_in or posedge clk_in) begin
if (sw_in) begin
    count <= count + 2'd01;
    sw_out <= sw_in;
end // end if 1
if (clk_in) begin
    if (count >= 2'd10) begin
        clk_out <= clk_in;
    end
end // end if 2
    
end // end always
endmodule

Do I need to reset the sw_out and clk_out to 0 after they pass through?

Altera_Forum · ‎04-27-2013

I suggest to refer to the Quartus template of a synchronous counter

always @ (posedge clk or posedge reset)
begin
  if (reset)
    count <= 0;
  else if (enable == 1'b1)
    count <= count + 1;
  end

You are trying to make an asynchronous counter which isn't synthesizable.

Altera_Forum · ‎04-30-2013

I'm not really following what you are trying to do because you are relating it to your code which can't be synthesized for starters. Just describe the problem you are trying to solve at a high level and we can point you in the right direction.